diff options
| author | Babu Moger <Babu.Moger@amd.com> | 2019-11-05 21:25:40 +0000 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2019-11-07 11:16:44 +0100 |
| commit | 9774a96f785bf0fa6d956ce33300463f1704dbeb (patch) | |
| tree | ea9c360eb714dcae64fab9b5222462113b924c21 /arch/x86/kernel/umip.c | |
| parent | b971880fe79f4042aaaf426744a5b19521bf77b3 (diff) | |
| download | lwn-9774a96f785bf0fa6d956ce33300463f1704dbeb.tar.gz lwn-9774a96f785bf0fa6d956ce33300463f1704dbeb.zip | |
x86/umip: Make the comments vendor-agnostic
AMD 2nd generation EPYC processors also support the UMIP feature. Make
the comments vendor-agnostic.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "x86@kernel.org" <x86@kernel.org>
Link: https://lkml.kernel.org/r/157298913784.17462.12654728938970637305.stgit@naples-babu.amd.com
Diffstat (limited to 'arch/x86/kernel/umip.c')
| -rw-r--r-- | arch/x86/kernel/umip.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c index 548fefed71ee..8ccef6c495dc 100644 --- a/arch/x86/kernel/umip.c +++ b/arch/x86/kernel/umip.c @@ -1,6 +1,6 @@ /* - * umip.c Emulation for instruction protected by the Intel User-Mode - * Instruction Prevention feature + * umip.c Emulation for instruction protected by the User-Mode Instruction + * Prevention feature * * Copyright (c) 2017, Intel Corporation. * Ricardo Neri <ricardo.neri-calderon@linux.intel.com> @@ -18,10 +18,10 @@ /** DOC: Emulation for User-Mode Instruction Prevention (UMIP) * - * The feature User-Mode Instruction Prevention present in recent Intel - * processor prevents a group of instructions (SGDT, SIDT, SLDT, SMSW and STR) - * from being executed with CPL > 0. Otherwise, a general protection fault is - * issued. + * User-Mode Instruction Prevention is a security feature present in recent + * x86 processors that, when enabled, prevents a group of instructions (SGDT, + * SIDT, SLDT, SMSW and STR) from being run in user mode by issuing a general + * protection fault if the instruction is executed with CPL > 0. * * Rather than relaying to the user space the general protection fault caused by * the UMIP-protected instructions (in the form of a SIGSEGV signal), it can be |