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| author | Nam Cao <namcao@linutronix.de> | 2025-05-11 23:17:56 +0200 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2025-09-16 18:46:44 -0600 |
| commit | d57676c21ef6f3dd530bcd7f5035a5e0b7699cc6 (patch) | |
| tree | d9e53c11addafb81a0c81ab25e88dbbe4fae34a3 /arch/riscv | |
| parent | 8f1ea7f04edd918b0e0fd8dc1318b22049a6c716 (diff) | |
| download | lwn-d57676c21ef6f3dd530bcd7f5035a5e0b7699cc6.tar.gz lwn-d57676c21ef6f3dd530bcd7f5035a5e0b7699cc6.zip | |
riscv: kprobes: Remove duplication of RV_EXTRACT_RS1_REG
Use RV_EXTRACT_RS1_REG instead of reimplementing its code.
Signed-off-by: Nam Cao <namcao@linutronix.de>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/linux-riscv/b441038c991da11a7a48ea7140ab00e3bb119387.1747215274.git.namcao@linutronix.de/
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/kernel/probes/simulate-insn.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/riscv/kernel/probes/simulate-insn.c b/arch/riscv/kernel/probes/simulate-insn.c index b76a691d0d9a..625d514c4ada 100644 --- a/arch/riscv/kernel/probes/simulate-insn.c +++ b/arch/riscv/kernel/probes/simulate-insn.c @@ -66,7 +66,7 @@ bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *reg unsigned long base_addr; u32 imm = (opcode >> 20) & 0xfff; u32 rd_index = (opcode >> 7) & 0x1f; - u32 rs1_index = (opcode >> 15) & 0x1f; + u32 rs1_index = RV_EXTRACT_RS1_REG(opcode); ret = rv_insn_reg_get_val(regs, rs1_index, &base_addr); if (!ret) @@ -115,9 +115,6 @@ bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *re return true; } -#define branch_rs1_idx(opcode) \ - (((opcode) >> 15) & 0x1f) - #define branch_imm(opcode) \ (((((opcode) >> 8) & 0xf ) << 1) | \ ((((opcode) >> 25) & 0x3f) << 5) | \ @@ -147,7 +144,7 @@ bool __kprobes simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *r unsigned long rs1_val; unsigned long rs2_val; - if (!rv_insn_reg_get_val(regs, branch_rs1_idx(opcode), &rs1_val) || + if (!rv_insn_reg_get_val(regs, RV_EXTRACT_RS1_REG(opcode), &rs1_val) || !rv_insn_reg_get_val(regs, RV_EXTRACT_RS2_REG(opcode), &rs2_val)) return false; |