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| author | Xiao Wang <xiao.w.wang@intel.com> | 2024-05-16 17:04:30 +0800 |
|---|---|---|
| committer | Daniel Borkmann <daniel@iogearbox.net> | 2024-05-24 16:53:12 +0200 |
| commit | c12603e76ef666ce5c51a9d6faf155c9e3de7601 (patch) | |
| tree | 82fb7b57e3cd4b398760b135b4a6c7e916e26037 /arch/riscv/Kconfig | |
| parent | ecec1887e24f11a3fcc391aa0f33fe0802be0804 (diff) | |
| download | lwn-c12603e76ef666ce5c51a9d6faf155c9e3de7601.tar.gz lwn-c12603e76ef666ce5c51a9d6faf155c9e3de7601.zip | |
riscv, bpf: Optimize zextw insn with Zba extension
The Zba extension provides add.uw insn which can be used to implement
zext.w with rs2 set as ZERO.
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Tested-by: Pu Lehui <pulehui@huawei.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Pu Lehui <pulehui@huawei.com>
Link: https://lore.kernel.org/bpf/20240516090430.493122-1-xiao.w.wang@intel.com
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9e87287942dc..6b8f1059594d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -595,6 +595,18 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb) depends on AS_HAS_OPTION_ARCH +config RISCV_ISA_ZBA + bool "Zba extension support for bit manipulation instructions" + default y + help + Add support for enabling optimisations in the kernel when the Zba + extension is detected at boot. + + The Zba extension provides instructions to accelerate the generation + of addresses that index into arrays of basic data types. + + If you don't know what to do here, say Y. + config RISCV_ISA_ZBB bool "Zbb extension support for bit manipulation instructions" depends on TOOLCHAIN_HAS_ZBB |