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authorPaul Mackerras <paulus@ozlabs.org>2018-03-20 08:46:13 +1100
committerMichael Ellerman <mpe@ellerman.id.au>2018-03-24 00:38:51 +1100
commit9bbf0b576d3294b6a2fda54d1af3b88290e8b65c (patch)
tree6d5327efb0de86a507b1607c4a3075a3d72455c7 /arch/powerpc/kernel/cpu_setup_6xx.S
parentdd0efb3f11cc0adcb4caa192ba09ad802d1fa6c0 (diff)
downloadlwn-9bbf0b576d3294b6a2fda54d1af3b88290e8b65c.tar.gz
lwn-9bbf0b576d3294b6a2fda54d1af3b88290e8b65c.zip
powerpc: Free up CPU feature bits on 64-bit machines
This moves all the CPU feature bits that are only used on 32-bit machines to the top 20 bits of the CPU feature word and arranges for them to be defined only in 32-bit builds. The features that are common to 32-bit and 64-bit machines are moved to bits 0-11 of the CPU feature word. This means that for 64-bit platforms, bits 44-63 can now be used for new features that only exist on 64-bit machines. (These bit numbers are counting from the right, i.e. the LSB is bit 0.) Because CPU_FTR_L3_DISABLE_NAP moved from the low 16 bits to the high 16 bits, we have to adjust some assembly code. Also, CPU_FTR_EMB_HV moved from the high 16 bits to the low 16 bits. Note that CPU_FTR_REAL_LE only applies to 64-bit chips, because only 64-bit chips (POWER6, 7, 8, 9) have a true little-endian mode that is a CPU execution mode as opposed to being a page attribute. With this we now have 20 free CPU feature bits on 64-bit machines. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel/cpu_setup_6xx.S')
-rw-r--r--arch/powerpc/kernel/cpu_setup_6xx.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
index c5e5a94d9892..a9f3970693e1 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -226,7 +226,7 @@ BEGIN_FTR_SECTION
beq 1f
END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
lwz r6,CPU_SPEC_FEATURES(r4)
- andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
+ andis. r0,r6,CPU_FTR_L3_DISABLE_NAP@h
beq 1f
li r7,CPU_FTR_CAN_NAP
andc r6,r6,r7