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| author | Nicholas Piggin <npiggin@gmail.com> | 2017-06-13 23:05:48 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-06-19 19:46:27 +1000 |
| commit | a9af97aa0a12c30178dd7ad9af8887d5b9c4647b (patch) | |
| tree | 463875705ded254aebad36ee4347c5eeba5b0846 /arch/powerpc/kernel/asm-offsets.c | |
| parent | 771d4304d07f080b6ce751e12f3579cb012a1b22 (diff) | |
| download | lwn-a9af97aa0a12c30178dd7ad9af8887d5b9c4647b.tar.gz lwn-a9af97aa0a12c30178dd7ad9af8887d5b9c4647b.zip | |
powerpc/64s: msgclr when handling doorbell exceptions from system reset
msgsnd doorbell exceptions are cleared when the doorbell interrupt is
taken. However if a doorbell exception causes a system reset interrupt
wake from power saving state, the message is not cleared. Processing
the doorbell from the system reset interrupt requires msgclr to avoid
taking the exception again.
Testing this plus the previous wakup direct patch gives:
original wakeup direct msgclr
Different threads, same core: 315k/s 264k/s 345k/s
Different cores: 235k/s 242k/s 242k/s
Net speedup is +10% for same core, and +3% for different core.
Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel/asm-offsets.c')
| -rw-r--r-- | arch/powerpc/kernel/asm-offsets.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index e15c178ba079..9624851ca276 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -746,6 +746,7 @@ int main(void) #endif DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER); + DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE); #ifdef CONFIG_PPC_8xx DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE)); |