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author | Christophe Leroy <christophe.leroy@c-s.fr> | 2018-12-10 11:41:29 +0000 |
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committer | Scott Wood <oss@buserror.net> | 2018-12-21 20:56:41 -0600 |
commit | 0deae39cec6dab3a66794f3e9e83ca4dc30080f1 (patch) | |
tree | 3368ae52860c4090f83eb991206ed4b4bc2098e7 /arch/powerpc/include/asm | |
parent | 01f45c8fb8b951e8d5cf648ce7ec16505ce303e7 (diff) | |
download | lwn-0deae39cec6dab3a66794f3e9e83ca4dc30080f1.tar.gz lwn-0deae39cec6dab3a66794f3e9e83ca4dc30080f1.zip |
powerpc/83xx: handle machine check caused by watchdog timer
When the watchdog timer is set in interrupt mode, it causes a
machine check when it times out. The purpose of this mode is to
ease debugging, not to crash the kernel and reboot the machine.
This patch implements a special handling for that, in order to not
crash the kernel if the watchdog times out while in interrupt or
within the idle task.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
[scottwood: added missing #include]
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r-- | arch/powerpc/include/asm/cputable.h | 1 | ||||
-rw-r--r-- | arch/powerpc/include/asm/reg.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index a0395ccbbe9e..d05f0c28e515 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -44,6 +44,7 @@ extern int machine_check_e500(struct pt_regs *regs); extern int machine_check_e200(struct pt_regs *regs); extern int machine_check_47x(struct pt_regs *regs); int machine_check_8xx(struct pt_regs *regs); +int machine_check_83xx(struct pt_regs *regs); extern void cpu_down_flush_e500v2(void); extern void cpu_down_flush_e500mc(void); diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 0d2139a0d5b9..1c98ef1f2d5b 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -769,6 +769,8 @@ #define SRR1_PROGTRAP 0x00020000 /* Trap */ #define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ +#define SRR1_MCE_MCP 0x00080000 /* Machine check signal caused interrupt */ + #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ #define HSRR1_DENORM 0x00100000 /* Denorm exception */ |