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| author | Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> | 2014-05-11 12:08:37 +0300 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-11-03 14:01:11 +0900 |
| commit | 91993c8c2ed52781a0f42bf7f40e28adc96e2bb2 (patch) | |
| tree | 4da05548436187fe5cc787f200284f16454fa584 /arch/openrisc/Kconfig | |
| parent | ddc92bec6d7d7e8a07794a8dbeade19476891b53 (diff) | |
| download | lwn-91993c8c2ed52781a0f42bf7f40e28adc96e2bb2.tar.gz lwn-91993c8c2ed52781a0f42bf7f40e28adc96e2bb2.zip | |
openrisc: use shadow registers to save regs on exception
Previously, the area between 0x0-0x100 have been used as a "scratch"
memory area to temporarily store regs during exception entry. In a
multi-core environment, this will not work.
This change is to use shadow registers for nested context.
Currently only the "critical" temp load/stores are covered, the
EMERGENCY_PRINT ones are left as is (when they are used, it's game over
anyway), they need to be handled as well in the future.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/Kconfig')
| -rw-r--r-- | arch/openrisc/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index a0f2e4a323c1..356dd67a86ea 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -124,6 +124,17 @@ config OPENRISC_NO_SPR_SR_DSX Say N here if you know that your OpenRISC processor has SPR_SR_DSX bit implemented. Say Y if you are unsure. +config OPENRISC_HAVE_SHADOW_GPRS + bool "Support for shadow gpr files" if !SMP + default y if SMP + help + Say Y here if your OpenRISC processor features shadowed + register files. They will in such case be used as a + scratch reg storage on exception entry. + + On SMP systems, this feature is mandatory. + On a unicore system it's safe to say N here if you are unsure. + config CMDLINE string "Default kernel command string" default "" |