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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-11-17 18:34:01 +0100 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-11-17 18:34:01 +0100 |
| commit | 8389a7b909f252e74ea92b2794de8d660cfee96e (patch) | |
| tree | a947f3080e953e4a44417389b3f2b69d4817be2e /arch/mips/fw | |
| parent | ad39b5a1ed68032292794b41a5f9e41ea69f8052 (diff) | |
| parent | 83cba933a6db1dd4d7ac85170f99461fbc339eff (diff) | |
| download | lwn-8389a7b909f252e74ea92b2794de8d660cfee96e.tar.gz lwn-8389a7b909f252e74ea92b2794de8d660cfee96e.zip | |
Merge tag 'spi-nor/for-5.5' into mtd/next
SPI NOR core changes:
- introduce 'struct spi_nor_controller_ops',
- clean the Register Operations methods,
- use dev_dbg insted of dev_err for low level info,
- fix retlen handling in sst_write(),
- fix silent truncations in spi_nor_read and spi_nor_read_raw(),
- fix the clearing of QE bit on lock()/unlock(),
- rework the disabling of the block write protection,
- rework the Quad Enable methods,
- make sure nor->spimem and nor->controller_ops are mutually exclusive,
- set default Quad Enable method for ISSI flashes,
- add support for few flashes.
SPI NOR controller drivers changes:
- intel-spi:
- support chips without software sequencer,
- add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
Diffstat (limited to 'arch/mips/fw')
| -rw-r--r-- | arch/mips/fw/arc/memory.c | 1 | ||||
| -rw-r--r-- | arch/mips/fw/sni/sniprom.c | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/arch/mips/fw/arc/memory.c b/arch/mips/fw/arc/memory.c index af44b35d79a1..b4328b3b5288 100644 --- a/arch/mips/fw/arc/memory.c +++ b/arch/mips/fw/arc/memory.c @@ -160,7 +160,6 @@ void __init prom_meminit(void) void __init prom_free_prom_memory(void) { - unsigned long addr; int i; if (prom_flags & PROM_FLAG_DONT_FREE_TEMP) diff --git a/arch/mips/fw/sni/sniprom.c b/arch/mips/fw/sni/sniprom.c index 8772617b64ce..80112f2298b6 100644 --- a/arch/mips/fw/sni/sniprom.c +++ b/arch/mips/fw/sni/sniprom.c @@ -43,7 +43,7 @@ /* O32 stack has to be 8-byte aligned. */ static u64 o32_stk[4096]; -#define O32_STK &o32_stk[sizeof(o32_stk)] +#define O32_STK (&o32_stk[ARRAY_SIZE(o32_stk)]) #define __PROM_O32(fun, arg) fun arg __asm__(#fun); \ __asm__(#fun " = call_o32") |