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| author | Bibo Mao <maobibo@loongson.cn> | 2026-02-06 09:27:46 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2026-02-06 09:27:46 +0800 |
| commit | c5cb12b81a0bddbff0f963662f18747b6d633592 (patch) | |
| tree | 513ccf1113859b05c86a30448ef55c67e1115ba7 /arch/loongarch/include | |
| parent | c2f94dafe197961f266fef8946d39df66a9750f4 (diff) | |
| download | lwn-c5cb12b81a0bddbff0f963662f18747b6d633592.tar.gz lwn-c5cb12b81a0bddbff0f963662f18747b6d633592.zip | |
LoongArch: KVM: Handle LOONGARCH_CSR_IPR during vCPU context switch
Register LOONGARCH_CSR_IPR is interrupt priority setting for nested
interrupt handling. Though LoongArch Linux AVEC driver does not use
this register, KVM hypervisor needs to save and restore this it during
vCPU context switch. Because Linux AVEC driver may use this register
in future, or other OS may use it.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include')
| -rw-r--r-- | arch/loongarch/include/asm/loongarch.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h index 553c4dc7a156..2a6bc99177d8 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -690,6 +690,7 @@ #define LOONGARCH_CSR_ISR3 0xa3 #define LOONGARCH_CSR_IRR 0xa4 +#define LOONGARCH_CSR_IPR 0xa5 #define LOONGARCH_CSR_PRID 0xc0 |