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| author | Kefeng Wang <wangkefeng.wang@huawei.com> | 2024-09-23 21:13:51 +0800 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2024-10-16 12:01:53 +0100 |
| commit | a923705c69f7f4ebe6a5488c1f556bed12d28031 (patch) | |
| tree | c51eb05da42a4a0caceabf0c250a18f2e6c7e68f /arch/loongarch/crypto/crc32-loongarch.c | |
| parent | 7ffc13e233951f15728c9d09db3cc8d9f6cf81f2 (diff) | |
| download | lwn-a923705c69f7f4ebe6a5488c1f556bed12d28031.tar.gz lwn-a923705c69f7f4ebe6a5488c1f556bed12d28031.zip | |
arm64: optimize flush tlb kernel range
Currently the kernel TLBs is flushed page by page if the target
VA range is less than MAX_DVM_OPS * PAGE_SIZE, otherwise we'll
brutally issue a TLBI ALL.
But we could optimize it when CPU supports TLB range operations,
convert to use __flush_tlb_range_op() like other tlb range flush
to improve performance.
Co-developed-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20240923131351.713304-3-wangkefeng.wang@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/loongarch/crypto/crc32-loongarch.c')
0 files changed, 0 insertions, 0 deletions