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| author | Wei-Lin Chang <weilin.chang@arm.com> | 2026-05-05 15:47:35 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2026-05-06 17:08:39 +0100 |
| commit | 8d9b9d985ad3a81c751a6b97edaf1d3c0780af7c (patch) | |
| tree | 98d471fec989179e40f80d8ceab58b336f88d656 /arch/arm64/include/asm | |
| parent | 1f7305d87aa23db2579df222eba504a333c2c978 (diff) | |
| download | lwn-8d9b9d985ad3a81c751a6b97edaf1d3c0780af7c.tar.gz lwn-8d9b9d985ad3a81c751a6b97edaf1d3c0780af7c.zip | |
KVM: arm64: nv: Consider the DS bit when translating TCR_EL2
When running an nVHE L1, TCR_EL2 is mapped to TCR_EL1. Writes to the
register are trapped and written to TCR_EL1 after a translation.
Booting an nVHE L1 with 52-bit VA isn't working because the translation
was ignoring the DS bit set by the guest, hence causing repeating level
0 faults. Add it in the translation function.
Signed-off-by: Wei-Lin Chang <weilin.chang@arm.com>
Link: https://patch.msgid.link/20260505144735.1496530-1-weilin.chang@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm')
| -rw-r--r-- | arch/arm64/include/asm/kvm_nested.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/kvm_nested.h index 091544e6af44..dc2957662ff2 100644 --- a/arch/arm64/include/asm/kvm_nested.h +++ b/arch/arm64/include/asm/kvm_nested.h @@ -23,6 +23,7 @@ static inline u64 tcr_el2_ps_to_tcr_el1_ips(u64 tcr_el2) static inline u64 translate_tcr_el2_to_tcr_el1(u64 tcr) { return TCR_EPD1_MASK | /* disable TTBR1_EL1 */ + ((tcr & TCR_EL2_DS) ? TCR_DS : 0) | ((tcr & TCR_EL2_TBI) ? TCR_TBI0 : 0) | tcr_el2_ps_to_tcr_el1_ips(tcr) | (tcr & TCR_EL2_TG0_MASK) | |