diff options
| author | Vladimir Barinov <vladimir.barinov@cogentembedded.com> | 2016-08-31 13:02:49 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-09-06 12:57:24 +0200 |
| commit | af111bce5437c6d4174434c9f5002f463f83d651 (patch) | |
| tree | a8a3417ea8154b4df068690310fe8726a4a59c80 /arch/arm64/boot/dts/renesas | |
| parent | b10690d11fead70652c2544098e41436258ec443 (diff) | |
| download | lwn-af111bce5437c6d4174434c9f5002f463f83d651.tar.gz lwn-af111bce5437c6d4174434c9f5002f463f83d651.zip | |
arm64: dts: h3ulcb: enable SCIF clk and pins
This enables the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index ecb9e1102266..67ce368ff9ee 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -37,10 +37,18 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; }; &scif2 { @@ -49,3 +57,8 @@ status = "okay"; }; + +&scif_clk { + clock-frequency = <14745600>; + status = "okay"; +}; |