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authorTakashi Iwai <tiwai@suse.de>2023-06-26 15:23:15 +0200
committerTakashi Iwai <tiwai@suse.de>2023-06-26 15:23:23 +0200
commita15b51375684c2bfa6017bb185139477e7a3b96c (patch)
tree6a4d7b4e7f09b858782cf2e5c0601d9f778cab15 /arch/arm/vfp/vfphw.S
parente94f1f96f108ba96c0ed8bf3fbdd8ee6a6703880 (diff)
parent4e0871333661d2ec0ed3dc00a945c2160eccae77 (diff)
downloadlwn-a15b51375684c2bfa6017bb185139477e7a3b96c.tar.gz
lwn-a15b51375684c2bfa6017bb185139477e7a3b96c.zip
Merge branch 'for-next' into for-linus
Pull the 6.5-devel branch for upstreaming. Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'arch/arm/vfp/vfphw.S')
-rw-r--r--arch/arm/vfp/vfphw.S6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 4d8478264d82..a4610d0f3215 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -172,13 +172,14 @@ vfp_hw_state_valid:
@ out before setting an FPEXC that
@ stops us reading stuff
VFPFMXR FPEXC, r1 @ Restore FPEXC last
+ mov sp, r3 @ we think we have handled things
+ pop {lr}
sub r2, r2, #4 @ Retry current instruction - if Thumb
str r2, [sp, #S_PC] @ mode it's two 16-bit instructions,
@ else it's one 32-bit instruction, so
@ always subtract 4 from the following
@ instruction address.
- mov lr, r3 @ we think we have handled things
local_bh_enable_and_ret:
adr r0, .
mov r1, #SOFTIRQ_DISABLE_OFFSET
@@ -209,8 +210,9 @@ skip:
process_exception:
DBGSTR "bounce"
+ mov sp, r3 @ setup for a return to the user code.
+ pop {lr}
mov r2, sp @ nothing stacked - regdump is at TOS
- mov lr, r3 @ setup for a return to the user code.
@ Now call the C code to package up the bounce to the support code
@ r0 holds the trigger instruction