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| author | Joseph Lo <josephl@nvidia.com> | 2012-11-13 10:04:48 +0800 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-11-15 15:09:22 -0700 |
| commit | 29a0e7beab8e05be53d5b9c050253a4dc417041e (patch) | |
| tree | eddaa429e909f209cb0628b0733e0ade8e277fd0 /arch/arm/mach-tegra/pm.h | |
| parent | d552920a02759cdc45d8507868de10ac2f5b9a18 (diff) | |
| download | lwn-29a0e7beab8e05be53d5b9c050253a4dc417041e.tar.gz lwn-29a0e7beab8e05be53d5b9c050253a4dc417041e.zip | |
ARM: tegra: retain L2 content over CPU suspend/resume
The L2 RAM is in different power domain from the CPU cluster. So the
L2 content can be retained over CPU suspend/resume. To do that, we
need to disable L2 after the MMU is disabled, and enable L2 before
the MMU is enabled. But the L2 controller is in the same power domain
with the CPU cluster. We need to restore it's settings and re-enable
it after the power be resumed.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm.h')
| -rw-r--r-- | arch/arm/mach-tegra/pm.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 512345c9eec3..787335cc964c 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -21,6 +21,8 @@ #ifndef _MACH_TEGRA_PM_H_ #define _MACH_TEGRA_PM_H_ +extern unsigned long l2x0_saved_regs_addr; + void save_cpu_arch_register(void); void restore_cpu_arch_register(void); |