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| author | Senthilvadivu Guruswamy <svadivu@ti.com> | 2011-01-24 06:21:58 +0000 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-03-11 15:46:19 +0200 |
| commit | 8b9cb3a8f39d0864c925c5cd5c2c54cfd85ad551 (patch) | |
| tree | b7ebabcc80701ace88f0ee305d84fb2d24650ecd /arch/arm/mach-omap2/clock2420_data.c | |
| parent | 96c401bcb83a182a4f332f2f64ee6530ba35511a (diff) | |
| download | lwn-8b9cb3a8f39d0864c925c5cd5c2c54cfd85ad551.tar.gz lwn-8b9cb3a8f39d0864c925c5cd5c2c54cfd85ad551.zip | |
OMAP2, 3: DSS2: Move clocks from core driver to dss driver
All clock management is moved to dss platform driver. clk_get/put APIs use
dss device instead of core platform device.
Hwmod adaptation design requires each of the DSS HW IP to be a platform driver.
So the device name is changed from omapdss to omapdss_dss in 2420, 2430,
3xxx clock database files. Now the core driver "omapdss" only takes care
of panel registration with the custom bus.
core driver also uses the clk_enable() / clk_disable() APIs exposed by DSS for
clock management.
DSS driver would do clock management of clocks needed by DISPC, RFBI, DSI, VENC
TODO: The clock content would be adapted to omap_hwmod in a seperate series.
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock2420_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock2420_data.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 0a992bc8d0d8..9ece62a44a3f 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1786,10 +1786,10 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), /* DSS domain clocks */ - CLK("omapdss", "ick", &dss_ick, CK_242X), - CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), - CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), - CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), + CLK("omapdss_dss", "ick", &dss_ick, CK_242X), + CLK("omapdss_dss", "dss1_fck", &dss1_fck, CK_242X), + CLK("omapdss_dss", "dss2_fck", &dss2_fck, CK_242X), + CLK("omapdss_dss", "tv_fck", &dss_54m_fck, CK_242X), /* L3 domain clocks */ CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), |