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authorShawn Guo <shawn.guo@linaro.org>2011-12-30 16:16:07 +0800
committerShawn Guo <shawn.guo@linaro.org>2011-12-30 16:16:07 +0800
commit5b2acf384c8a8707d32a98106192ee7187e4446d (patch)
tree568cc0c99cc25e0003c26e62e50f94ce5c2bd2eb /arch/arm/mach-imx
parent5f0a6e2d503896062f641639dacfe5055c2f593b (diff)
downloadlwn-5b2acf384c8a8707d32a98106192ee7187e4446d.tar.gz
lwn-5b2acf384c8a8707d32a98106192ee7187e4446d.zip
ARM: imx6: fix v7_invalidate_l1 by adding I-Cache invalidation
The recent suspend/resume and reset testing on imx6q discovers that not only D-Cache but also I-Cache has random data and validity when the core comes out of a power recycle. This patch adds I-Cache invalidation into v7_invalidate_l1 to make sure both D-Cache and I-Cache invalidated on power-up. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/head-v7.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S
index 6229efbc70cb..c844112061be 100644
--- a/arch/arm/mach-imx/head-v7.S
+++ b/arch/arm/mach-imx/head-v7.S
@@ -33,6 +33,7 @@
*/
ENTRY(v7_invalidate_l1)
mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
mcr p15, 2, r0, c0, c0, 0
mrc p15, 1, r0, c0, c0, 0