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authorChanghwan Youn <chaos.youn@samsung.com>2011-10-04 17:08:56 +0900
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 18:35:01 +0900
commite6a275a8f92392f27e3accd6182d52627ef37258 (patch)
tree3d509a20f244648a439ab15d30abd2c743ed70d2 /arch/arm/mach-exynos4/cpu.c
parent3a062281129229b50e06547af3110f8eccd2f4e4 (diff)
downloadlwn-e6a275a8f92392f27e3accd6182d52627ef37258.tar.gz
lwn-e6a275a8f92392f27e3accd6182d52627ef37258.zip
ARM: EXYNOS4: Add support new EXYNOS4412 SoC
This patch adds Samsung EXYNOS4412 SoC support. The EXYNOS4412 integrates a ARM Cortex A9 quad-core. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4/cpu.c')
-rw-r--r--arch/arm/mach-exynos4/cpu.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 35fe8421bc34..940bc12f7547 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -191,7 +191,7 @@ void __init exynos4_init_clocks(int xtal)
if (soc_is_exynos4210())
exynos4210_register_clocks();
- else if (soc_is_exynos4212())
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
exynos4212_register_clocks();
exynos4_register_clocks();
@@ -255,7 +255,7 @@ static int __init exynos4_l2x0_cache_init(void)
if (soc_is_exynos4210())
__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
- else if (soc_is_exynos4212())
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
/* L2X0 Prefetch Control */