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authorChanghwan Youn <chaos.youn@samsung.com>2011-10-04 17:02:58 +0900
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 18:34:59 +0900
commit637c2afa57ec9cd0ddc8879ea0cda4d8835ba71d (patch)
tree6197343d6c335c7b682b70dac173c1b39e171a53 /arch/arm/mach-exynos4/cpu.c
parent1abd328ee5e2e870fa035e7882e7a278127b4ccf (diff)
downloadlwn-637c2afa57ec9cd0ddc8879ea0cda4d8835ba71d.tar.gz
lwn-637c2afa57ec9cd0ddc8879ea0cda4d8835ba71d.zip
ARM: EXYNOS4: Add support PPI in external GIC
To support PPI in external GIC of EXYNOS4 SoCs, gic_arch_extn.irq_eoi, irq_unmask and irq_mask are fixed. This patch is necessary because external GIC of EXYNOS4 cannot support register banking. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4/cpu.c')
-rw-r--r--arch/arm/mach-exynos4/cpu.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 02ec52a99274..35fe8421bc34 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -198,20 +198,25 @@ void __init exynos4_init_clocks(int xtal)
exynos4_setup_clocks();
}
-static void exynos4_gic_irq_eoi(struct irq_data *d)
+static void exynos4_gic_irq_fix_base(struct irq_data *d)
{
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
gic_data->cpu_base = S5P_VA_GIC_CPU +
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+
+ gic_data->dist_base = S5P_VA_GIC_DIST +
+ (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
}
void __init exynos4_init_irq(void)
{
int irq;
- gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
- gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
+ gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+ gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
+ gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
+ gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {