summaryrefslogtreecommitdiff
path: root/arch/arm/mach-clps711x
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 13:43:38 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 13:43:38 -0700
commit3883cbb6c1bda013a3ce2dbdab7dc97c52e4a232 (patch)
tree5b69f83b049d24ac81123ac954ca8c9128e48443 /arch/arm/mach-clps711x
parentd2033f2c1d1de2239ded15e478ddb4028f192a15 (diff)
parent1eb92b24e243085d242cf5ffd64829bba70972e1 (diff)
downloadlwn-3883cbb6c1bda013a3ce2dbdab7dc97c52e4a232.tar.gz
lwn-3883cbb6c1bda013a3ce2dbdab7dc97c52e4a232.zip
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC specific changes from Arnd Bergmann: "These changes are all to SoC-specific code, a total of 33 branches on 17 platforms were pulled into this. Like last time, Renesas sh-mobile is now the platform with the most changes, followed by OMAP and EXYNOS. Two new platforms, TI Keystone and Rockchips RK3xxx are added in this branch, both containing almost no platform specific code at all, since they are using generic subsystem interfaces for clocks, pinctrl, interrupts etc. The device drivers are getting merged through the respective subsystem maintainer trees. One more SoC (u300) is now multiplatform capable and several others (shmobile, exynos, msm, integrator, kirkwood, clps711x) are moving towards that goal with this series but need more work. Also noteworthy is the work on PCI here, which is traditionally part of the SoC specific code. With the changes done by Thomas Petazzoni, we can now more easily have PCI host controller drivers as loadable modules and keep them separate from the platform code in drivers/pci/host. This has already led to the discovery that three platforms (exynos, spear and imx) are actually using an identical PCIe host controller and will be able to share a driver once support for spear and imx is added." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (480 commits) ARM: integrator: let pciv3 use mem/premem from device tree ARM: integrator: set local side PCI addresses right ARM: dts: Add pcie controller node for exynos5440-ssdk5440 ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC ARM: EXYNOS: Enable PCIe support for Exynos5440 pci: Add PCIe driver for Samsung Exynos ARM: OMAP5: voltagedomain data: remove temporary OMAP4 voltage data ARM: keystone: Move CPU bringup code to dedicated asm file ARM: multiplatform: always pick one CPU type ARM: imx: select syscon for IMX6SL ARM: keystone: select ARM_ERRATA_798181 only for SMP ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1 ARM: OMAP2+: AM43x: resolve SMP related build error dmaengine: edma: enable build for AM33XX ARM: edma: Add EDMA crossbar event mux support ARM: edma: Add DT and runtime PM support to the private EDMA API dmaengine: edma: Add TI EDMA device tree binding arm: add basic support for Rockchip RK3066a boards arm: add debug uarts for rockchip rk29xx and rk3xxx series arm: Add basic clocks for Rockchip rk3066a SoCs ...
Diffstat (limited to 'arch/arm/mach-clps711x')
-rw-r--r--arch/arm/mach-clps711x/Kconfig3
-rw-r--r--arch/arm/mach-clps711x/Makefile5
-rw-r--r--arch/arm/mach-clps711x/board-autcpu12.c133
-rw-r--r--arch/arm/mach-clps711x/board-cdb89712.c3
-rw-r--r--arch/arm/mach-clps711x/board-clep7312.c1
-rw-r--r--arch/arm/mach-clps711x/board-edb7211.c34
-rw-r--r--arch/arm/mach-clps711x/board-fortunet.c1
-rw-r--r--arch/arm/mach-clps711x/board-p720t.c254
-rw-r--r--arch/arm/mach-clps711x/common.c89
-rw-r--r--arch/arm/mach-clps711x/common.h1
-rw-r--r--arch/arm/mach-clps711x/devices.c68
-rw-r--r--arch/arm/mach-clps711x/devices.h12
-rw-r--r--arch/arm/mach-clps711x/include/mach/autcpu12.h59
-rw-r--r--arch/arm/mach-clps711x/include/mach/clps711x.h88
-rw-r--r--arch/arm/mach-clps711x/include/mach/hardware.h7
-rw-r--r--arch/arm/mach-clps711x/include/mach/memory.h41
-rw-r--r--arch/arm/mach-clps711x/include/mach/syspld.h116
17 files changed, 499 insertions, 416 deletions
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 2d00165e85ec..01ad4d41e728 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -22,8 +22,7 @@ config ARCH_CLEP7312
config ARCH_EDB7211
bool "EDB7211"
- select ARCH_SELECT_MEMORY_MODEL
- select ARCH_SPARSEMEM_ENABLE
+ select ARCH_HAS_HOLES_MEMORYMODEL
help
Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
evaluation board.
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 992995af666a..f30ed2b496fb 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -4,10 +4,7 @@
# Object file lists.
-obj-y := common.o
-obj-m :=
-obj-n :=
-obj- :=
+obj-y := common.o devices.o
obj-$(CONFIG_ARCH_AUTCPU12) += board-autcpu12.o
obj-$(CONFIG_ARCH_CDB89712) += board-cdb89712.o
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index f38584709df7..5867aebd8d0c 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -26,6 +26,8 @@
#include <linux/gpio.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand-gpio.h>
#include <linux/platform_device.h>
@@ -40,38 +42,49 @@
#include <asm/page.h>
#include <asm/mach/map.h>
-#include <mach/autcpu12.h>
#include "common.h"
+#include "devices.h"
-#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300)
-#define AUTCPU12_CS8900_IRQ (IRQ_EINT3)
+/* NOR flash */
+#define AUTCPU12_FLASH_BASE (CS0_PHYS_BASE)
+
+/* Board specific hardware definitions */
+#define AUTCPU12_CHAR_LCD_BASE (CS1_PHYS_BASE + 0x00000000)
+#define AUTCPU12_CSAUX1_BASE (CS1_PHYS_BASE + 0x04000000)
+#define AUTCPU12_CAN_BASE (CS1_PHYS_BASE + 0x08000000)
+#define AUTCPU12_TOUCH_BASE (CS1_PHYS_BASE + 0x0a000000)
+#define AUTCPU12_IO_BASE (CS1_PHYS_BASE + 0x0c000000)
+#define AUTCPU12_LPT_BASE (CS1_PHYS_BASE + 0x0e000000)
+
+/* NVRAM */
+#define AUTCPU12_NVRAM_BASE (CS1_PHYS_BASE + 0x02000000)
+/* SmartMedia flash */
#define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000)
#define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10)
+/* Ethernet */
+#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300)
+#define AUTCPU12_CS8900_IRQ (IRQ_EINT3)
+
+/* NAND flash */
#define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO)
#define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
#define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
#define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3)
+/* LCD contrast digital potentiometer */
+#define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0)
+#define AUTCPU12_DPOT_CLK CLPS711X_GPIO(4, 1)
+#define AUTCPU12_DPOT_UD CLPS711X_GPIO(4, 2)
+
static struct resource autcpu12_cs8900_resource[] __initdata = {
DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
};
-static struct resource autcpu12_nvram_resource[] __initdata = {
- DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
-};
-
-static struct platform_device autcpu12_nvram_pdev __initdata = {
- .name = "autcpu12_nvram",
- .id = -1,
- .resource = autcpu12_nvram_resource,
- .num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
-};
-
static struct resource autcpu12_nand_resource[] __initdata = {
DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
};
@@ -147,17 +160,106 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = {
},
};
+static const struct gpio autcpu12_gpios[] __initconst = {
+ { AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" },
+ { AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" },
+ { AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" },
+};
+
+static struct mtd_partition autcpu12_flash_partitions[] = {
+ {
+ .name = "NOR.0",
+ .offset = 0,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static struct physmap_flash_data autcpu12_flash_pdata = {
+ .width = 4,
+ .parts = autcpu12_flash_partitions,
+ .nr_parts = ARRAY_SIZE(autcpu12_flash_partitions),
+};
+
+static struct resource autcpu12_flash_resources[] __initdata = {
+ DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M),
+};
+
+static struct platform_device autcpu12_flash_pdev __initdata = {
+ .name = "physmap-flash",
+ .id = 0,
+ .resource = autcpu12_flash_resources,
+ .num_resources = ARRAY_SIZE(autcpu12_flash_resources),
+ .dev = {
+ .platform_data = &autcpu12_flash_pdata,
+ },
+};
+
+static struct resource autcpu12_nvram_resource[] __initdata = {
+ DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0),
+};
+
+static struct platdata_mtd_ram autcpu12_nvram_pdata = {
+ .bankwidth = 4,
+};
+
+static struct platform_device autcpu12_nvram_pdev __initdata = {
+ .name = "mtd-ram",
+ .id = 0,
+ .resource = autcpu12_nvram_resource,
+ .num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
+ .dev = {
+ .platform_data = &autcpu12_nvram_pdata,
+ },
+};
+
+static void __init autcpu12_nvram_init(void)
+{
+ void __iomem *nvram;
+ unsigned int save[2];
+ resource_size_t nvram_size = SZ_128K;
+
+ /*
+ * Check for 32K/128K
+ * Read ofs 0K
+ * Read ofs 64K
+ * Write complement to ofs 64K
+ * Read and check result on ofs 0K
+ * Restore contents
+ */
+ nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K);
+ if (nvram) {
+ save[0] = readl(nvram + 0);
+ save[1] = readl(nvram + SZ_64K);
+ writel(~save[0], nvram + SZ_64K);
+ if (readl(nvram + 0) != save[0]) {
+ writel(save[0], nvram + 0);
+ nvram_size = SZ_32K;
+ } else
+ writel(save[1], nvram + SZ_64K);
+ iounmap(nvram);
+
+ autcpu12_nvram_resource[0].end =
+ autcpu12_nvram_resource[0].start + nvram_size - 1;
+ platform_device_register(&autcpu12_nvram_pdev);
+ } else
+ pr_err("Failed to remap NVRAM resource\n");
+}
+
static void __init autcpu12_init(void)
{
+ clps711x_devices_init();
+ platform_device_register(&autcpu12_flash_pdev);
platform_device_register_simple("video-clps711x", 0, NULL, 0);
platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
ARRAY_SIZE(autcpu12_cs8900_resource));
platform_device_register(&autcpu12_mmgpio_pdev);
- platform_device_register(&autcpu12_nvram_pdev);
+ autcpu12_nvram_init();
}
static void __init autcpu12_init_late(void)
{
+ gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
+
if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
/* We are need both drivers to handle NAND */
platform_device_register(&autcpu12_nand_pdev);
@@ -169,6 +271,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
.atag_offset = 0x20000,
.nr_irqs = CLPS711X_NR_IRQS,
.map_io = clps711x_map_io,
+ .init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.init_machine = autcpu12_init,
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index baab7da33c9b..a9e38c6bcfb4 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -39,6 +39,7 @@
#include <asm/mach/map.h>
#include "common.h"
+#include "devices.h"
#define CDB89712_CS8900_BASE (CS2_PHYS_BASE + 0x300)
#define CDB89712_CS8900_IRQ (IRQ_EINT3)
@@ -127,6 +128,7 @@ static struct platform_device cdb89712_sram_pdev __initdata = {
static void __init cdb89712_init(void)
{
+ clps711x_devices_init();
platform_device_register(&cdb89712_flash_pdev);
platform_device_register(&cdb89712_bootrom_pdev);
platform_device_register(&cdb89712_sram_pdev);
@@ -139,6 +141,7 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712")
.atag_offset = 0x100,
.nr_irqs = CLPS711X_NR_IRQS,
.map_io = clps711x_map_io,
+ .init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.init_machine = cdb89712_init,
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index 014aa3c19a03..b4764246d0f8 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -39,6 +39,7 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
.nr_irqs = CLPS711X_NR_IRQS,
.fixup = fixup_clep7312,
.map_io = clps711x_map_io,
+ .init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.handle_irq = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 5f928e9ed2ef..9dfb990f0801 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -12,6 +12,7 @@
#include <linux/delay.h>
#include <linux/memblock.h>
#include <linux/types.h>
+#include <linux/i2c-gpio.h>
#include <linux/interrupt.h>
#include <linux/backlight.h>
#include <linux/platform_device.h>
@@ -29,6 +30,7 @@
#include <mach/hardware.h>
#include "common.h"
+#include "devices.h"
#define VIDEORAM_SIZE SZ_128K
@@ -36,11 +38,24 @@
#define EDB7211_LCDEN CLPS711X_GPIO(3, 2)
#define EDB7211_LCDBL CLPS711X_GPIO(3, 3)
+#define EDB7211_I2C_SDA CLPS711X_GPIO(3, 4)
+#define EDB7211_I2C_SCL CLPS711X_GPIO(3, 5)
+
#define EDB7211_FLASH0_BASE (CS0_PHYS_BASE)
#define EDB7211_FLASH1_BASE (CS1_PHYS_BASE)
+
#define EDB7211_CS8900_BASE (CS2_PHYS_BASE + 0x300)
#define EDB7211_CS8900_IRQ (IRQ_EINT3)
+/* The extra 8 lines of the keyboard matrix */
+#define EDB7211_EXTKBD_BASE (CS3_PHYS_BASE)
+
+static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = {
+ .sda_pin = EDB7211_I2C_SDA,
+ .scl_pin = EDB7211_I2C_SCL,
+ .scl_is_output_only = 1,
+};
+
static struct resource edb7211_cs8900_resource[] __initdata = {
DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
@@ -94,13 +109,14 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = {
static void edb7211_lcd_backlight_set_intensity(int intensity)
{
- gpio_set_value(EDB7211_LCDBL, intensity);
+ gpio_set_value(EDB7211_LCDBL, !!intensity);
+ clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON);
}
static struct generic_bl_info edb7211_lcd_backlight_pdata = {
.name = "lcd-backlight.0",
.default_intensity = 0x01,
- .max_intensity = 0x01,
+ .max_intensity = 0x0f,
.set_bl_intensity = edb7211_lcd_backlight_set_intensity,
};
@@ -112,8 +128,8 @@ static struct gpio edb7211_gpios[] __initconst = {
static struct map_desc edb7211_io_desc[] __initdata = {
{ /* Memory-mapped extra keyboard row */
- .virtual = IO_ADDRESS(EP7211_PHYS_EXTKBD),
- .pfn = __phys_to_pfn(EP7211_PHYS_EXTKBD),
+ .virtual = IO_ADDRESS(EDB7211_EXTKBD_BASE),
+ .pfn = __phys_to_pfn(EDB7211_EXTKBD_BASE),
.length = SZ_1M,
.type = MT_DEVICE,
},
@@ -151,6 +167,11 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
static void __init edb7211_init(void)
{
+ clps711x_devices_init();
+}
+
+static void __init edb7211_init_late(void)
+{
gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
platform_device_register(&edb7211_flash_pdev);
@@ -163,6 +184,9 @@ static void __init edb7211_init(void)
platform_device_register_simple("video-clps711x", 0, NULL, 0);
platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
ARRAY_SIZE(edb7211_cs8900_resource));
+ platform_device_register_data(&platform_bus, "i2c-gpio", 0,
+ &edb7211_i2c_pdata,
+ sizeof(edb7211_i2c_pdata));
}
MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
@@ -172,9 +196,11 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
.fixup = fixup_edb7211,
.reserve = edb7211_reserve,
.map_io = edb7211_map_io,
+ .init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.init_machine = edb7211_init,
+ .init_late = edb7211_init_late,
.handle_irq = clps711x_handle_irq,
.restart = clps711x_restart,
MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c
index c5675efc8c6a..b1561e3d7c5c 100644
--- a/arch/arm/mach-clps711x/board-fortunet.c
+++ b/arch/arm/mach-clps711x/board-fortunet.c
@@ -77,6 +77,7 @@ MACHINE_START(FORTUNET, "ARM-FortuNet")
.nr_irqs = CLPS711X_NR_IRQS,
.fixup = fortunet_fixup,
.map_io = clps711x_map_io,
+ .init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.handle_irq = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 8d3ee6771135..dd81b06f68fe 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -23,10 +23,12 @@
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/io.h>
+#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/leds.h>
#include <linux/sizes.h>
#include <linux/backlight.h>
+#include <linux/basic_mmio_gpio.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand-gpio.h>
@@ -38,11 +40,11 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/syspld.h>
#include <video/platform_lcd.h>
#include "common.h"
+#include "devices.h"
#define P720T_USERLED CLPS711X_GPIO(3, 0)
#define P720T_NAND_CLE CLPS711X_GPIO(4, 0)
@@ -51,6 +53,178 @@
#define P720T_NAND_BASE (CLPS711X_SDRAM1_BASE)
+#define P720T_MMGPIO_BASE (CLPS711X_NR_GPIO)
+
+#define SYSPLD_PHYS_BASE IOMEM(CS1_PHYS_BASE)
+
+#define PLD_INT (SYSPLD_PHYS_BASE + 0x000000)
+#define PLD_INT_MMGPIO_BASE (P720T_MMGPIO_BASE + 0)
+#define PLD_INT_PENIRQ (PLD_INT_MMGPIO_BASE + 5)
+#define PLD_INT_UCB_IRQ (PLD_INT_MMGPIO_BASE + 1)
+#define PLD_INT_KBD_ATN (PLD_INT_MMGPIO_BASE + 0) /* EINT1 */
+
+#define PLD_PWR (SYSPLD_PHYS_BASE + 0x000004)
+#define PLD_PWR_MMGPIO_BASE (P720T_MMGPIO_BASE + 8)
+#define PLD_PWR_EXT (PLD_PWR_MMGPIO_BASE + 5)
+#define PLD_PWR_MODE (PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */
+#define PLD_S4_ON (PLD_PWR_MMGPIO_BASE + 3) /* LCD bias voltage enable */
+#define PLD_S3_ON (PLD_PWR_MMGPIO_BASE + 2) /* LCD backlight enable */
+#define PLD_S2_ON (PLD_PWR_MMGPIO_BASE + 1) /* LCD 3V3 supply enable */
+#define PLD_S1_ON (PLD_PWR_MMGPIO_BASE + 0) /* LCD 3V supply enable */
+
+#define PLD_KBD (SYSPLD_PHYS_BASE + 0x000008)
+#define PLD_KBD_MMGPIO_BASE (P720T_MMGPIO_BASE + 16)
+#define PLD_KBD_WAKE (PLD_KBD_MMGPIO_BASE + 1)
+#define PLD_KBD_EN (PLD_KBD_MMGPIO_BASE + 0)
+
+#define PLD_SPI (SYSPLD_PHYS_BASE + 0x00000c)
+#define PLD_SPI_MMGPIO_BASE (P720T_MMGPIO_BASE + 24)
+#define PLD_SPI_EN (PLD_SPI_MMGPIO_BASE + 0)
+
+#define PLD_IO (SYSPLD_PHYS_BASE + 0x000010)
+#define PLD_IO_MMGPIO_BASE (P720T_MMGPIO_BASE + 32)
+#define PLD_IO_BOOTSEL (PLD_IO_MMGPIO_BASE + 6) /* Boot sel switch */
+#define PLD_IO_USER (PLD_IO_MMGPIO_BASE + 5) /* User defined switch */
+#define PLD_IO_LED3 (PLD_IO_MMGPIO_BASE + 4)
+#define PLD_IO_LED2 (PLD_IO_MMGPIO_BASE + 3)
+#define PLD_IO_LED1 (PLD_IO_MMGPIO_BASE + 2)
+#define PLD_IO_LED0 (PLD_IO_MMGPIO_BASE + 1)
+#define PLD_IO_LEDEN (PLD_IO_MMGPIO_BASE + 0)
+
+#define PLD_IRDA (SYSPLD_PHYS_BASE + 0x000014)
+#define PLD_IRDA_MMGPIO_BASE (P720T_MMGPIO_BASE + 40)
+#define PLD_IRDA_EN (PLD_IRDA_MMGPIO_BASE + 0)
+
+#define PLD_COM2 (SYSPLD_PHYS_BASE + 0x000018)
+#define PLD_COM2_MMGPIO_BASE (P720T_MMGPIO_BASE + 48)
+#define PLD_COM2_EN (PLD_COM2_MMGPIO_BASE + 0)
+
+#define PLD_COM1 (SYSPLD_PHYS_BASE + 0x00001c)
+#define PLD_COM1_MMGPIO_BASE (P720T_MMGPIO_BASE + 56)
+#define PLD_COM1_EN (PLD_COM1_MMGPIO_BASE + 0)
+
+#define PLD_AUD (SYSPLD_PHYS_BASE + 0x000020)
+#define PLD_AUD_MMGPIO_BASE (P720T_MMGPIO_BASE + 64)
+#define PLD_AUD_DIV1 (PLD_AUD_MMGPIO_BASE + 6)
+#define PLD_AUD_DIV0 (PLD_AUD_MMGPIO_BASE + 5)
+#define PLD_AUD_CLK_SEL1 (PLD_AUD_MMGPIO_BASE + 4)
+#define PLD_AUD_CLK_SEL0 (PLD_AUD_MMGPIO_BASE + 3)
+#define PLD_AUD_MIC_PWR (PLD_AUD_MMGPIO_BASE + 2)
+#define PLD_AUD_MIC_GAIN (PLD_AUD_MMGPIO_BASE + 1)
+#define PLD_AUD_CODEC_EN (PLD_AUD_MMGPIO_BASE + 0)
+
+#define PLD_CF (SYSPLD_PHYS_BASE + 0x000024)
+#define PLD_CF_MMGPIO_BASE (P720T_MMGPIO_BASE + 72)
+#define PLD_CF2_SLEEP (PLD_CF_MMGPIO_BASE + 5)
+#define PLD_CF1_SLEEP (PLD_CF_MMGPIO_BASE + 4)
+#define PLD_CF2_nPDREQ (PLD_CF_MMGPIO_BASE + 3)
+#define PLD_CF1_nPDREQ (PLD_CF_MMGPIO_BASE + 2)
+#define PLD_CF2_nIRQ (PLD_CF_MMGPIO_BASE + 1)
+#define PLD_CF1_nIRQ (PLD_CF_MMGPIO_BASE + 0)
+
+#define PLD_SDC (SYSPLD_PHYS_BASE + 0x000028)
+#define PLD_SDC_MMGPIO_BASE (P720T_MMGPIO_BASE + 80)
+#define PLD_SDC_INT_EN (PLD_SDC_MMGPIO_BASE + 2)
+#define PLD_SDC_WP (PLD_SDC_MMGPIO_BASE + 1)
+#define PLD_SDC_CD (PLD_SDC_MMGPIO_BASE + 0)
+
+#define PLD_CODEC (SYSPLD_PHYS_BASE + 0x400000)
+#define PLD_CODEC_MMGPIO_BASE (P720T_MMGPIO_BASE + 88)
+#define PLD_CODEC_IRQ3 (PLD_CODEC_MMGPIO_BASE + 4)
+#define PLD_CODEC_IRQ2 (PLD_CODEC_MMGPIO_BASE + 3)
+#define PLD_CODEC_IRQ1 (PLD_CODEC_MMGPIO_BASE + 2)
+#define PLD_CODEC_EN (PLD_CODEC_MMGPIO_BASE + 0)
+
+#define PLD_BRITE (SYSPLD_PHYS_BASE + 0x400004)
+#define PLD_BRITE_MMGPIO_BASE (P720T_MMGPIO_BASE + 96)
+#define PLD_BRITE_UP (PLD_BRITE_MMGPIO_BASE + 1)
+#define PLD_BRITE_DN (PLD_BRITE_MMGPIO_BASE + 0)
+
+#define PLD_LCDEN (SYSPLD_PHYS_BASE + 0x400008)
+#define PLD_LCDEN_MMGPIO_BASE (P720T_MMGPIO_BASE + 104)
+#define PLD_LCDEN_EN (PLD_LCDEN_MMGPIO_BASE + 0)
+
+#define PLD_TCH (SYSPLD_PHYS_BASE + 0x400010)
+#define PLD_TCH_MMGPIO_BASE (P720T_MMGPIO_BASE + 112)
+#define PLD_TCH_PENIRQ (PLD_TCH_MMGPIO_BASE + 1)
+#define PLD_TCH_EN (PLD_TCH_MMGPIO_BASE + 0)
+
+#define PLD_GPIO (SYSPLD_PHYS_BASE + 0x400014)
+#define PLD_GPIO_MMGPIO_BASE (P720T_MMGPIO_BASE + 120)
+#define PLD_GPIO2 (PLD_GPIO_MMGPIO_BASE + 2)
+#define PLD_GPIO1 (PLD_GPIO_MMGPIO_BASE + 1)
+#define PLD_GPIO0 (PLD_GPIO_MMGPIO_BASE + 0)
+
+static struct gpio p720t_gpios[] __initconst = {
+ { PLD_S1_ON, GPIOF_OUT_INIT_LOW, "PLD_S1_ON" },
+ { PLD_S2_ON, GPIOF_OUT_INIT_LOW, "PLD_S2_ON" },
+ { PLD_S3_ON, GPIOF_OUT_INIT_LOW, "PLD_S3_ON" },
+ { PLD_S4_ON, GPIOF_OUT_INIT_LOW, "PLD_S4_ON" },
+ { PLD_KBD_EN, GPIOF_OUT_INIT_LOW, "PLD_KBD_EN" },
+ { PLD_SPI_EN, GPIOF_OUT_INIT_LOW, "PLD_SPI_EN" },
+ { PLD_IO_USER, GPIOF_OUT_INIT_LOW, "PLD_IO_USER" },
+ { PLD_IO_LED0, GPIOF_OUT_INIT_LOW, "PLD_IO_LED0" },
+ { PLD_IO_LED1, GPIOF_OUT_INIT_LOW, "PLD_IO_LED1" },
+ { PLD_IO_LED2, GPIOF_OUT_INIT_LOW, "PLD_IO_LED2" },
+ { PLD_IO_LED3, GPIOF_OUT_INIT_LOW, "PLD_IO_LED3" },
+ { PLD_IO_LEDEN, GPIOF_OUT_INIT_LOW, "PLD_IO_LEDEN" },
+ { PLD_IRDA_EN, GPIOF_OUT_INIT_LOW, "PLD_IRDA_EN" },
+ { PLD_COM1_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM1_EN" },
+ { PLD_COM2_EN, GPIOF_OUT_INIT_HIGH, "PLD_COM2_EN" },
+ { PLD_CODEC_EN, GPIOF_OUT_INIT_LOW, "PLD_CODEC_EN" },
+ { PLD_LCDEN_EN, GPIOF_OUT_INIT_LOW, "PLD_LCDEN_EN" },
+ { PLD_TCH_EN, GPIOF_OUT_INIT_LOW, "PLD_TCH_EN" },
+ { P720T_USERLED,GPIOF_OUT_INIT_LOW, "USER_LED" },
+};
+
+static struct resource p720t_mmgpio_resource[] __initdata = {
+ DEFINE_RES_MEM_NAMED(0, 4, "dat"),
+};
+
+static struct bgpio_pdata p720t_mmgpio_pdata = {
+ .ngpio = 8,
+};
+
+static struct platform_device p720t_mmgpio __initdata = {
+ .name = "basic-mmio-gpio",
+ .id = -1,
+ .resource = p720t_mmgpio_resource,
+ .num_resources = ARRAY_SIZE(p720t_mmgpio_resource),
+ .dev = {
+ .platform_data = &p720t_mmgpio_pdata,
+ },
+};
+
+static void __init p720t_mmgpio_init(void __iomem *addrbase, int gpiobase)
+{
+ p720t_mmgpio_resource[0].start = (unsigned long)addrbase;
+ p720t_mmgpio_pdata.base = gpiobase;
+
+ platform_device_register(&p720t_mmgpio);
+}
+
+static struct {
+ void __iomem *addrbase;
+ int gpiobase;
+} mmgpios[] __initconst = {
+ { PLD_INT, PLD_INT_MMGPIO_BASE },
+ { PLD_PWR, PLD_PWR_MMGPIO_BASE },
+ { PLD_KBD, PLD_KBD_MMGPIO_BASE },
+ { PLD_SPI, PLD_SPI_MMGPIO_BASE },
+ { PLD_IO, PLD_IO_MMGPIO_BASE },
+ { PLD_IRDA, PLD_IRDA_MMGPIO_BASE },
+ { PLD_COM2, PLD_COM2_MMGPIO_BASE },
+ { PLD_COM1, PLD_COM1_MMGPIO_BASE },
+ { PLD_AUD, PLD_AUD_MMGPIO_BASE },
+ { PLD_CF, PLD_CF_MMGPIO_BASE },
+ { PLD_SDC, PLD_SDC_MMGPIO_BASE },
+ { PLD_CODEC, PLD_CODEC_MMGPIO_BASE },
+ { PLD_BRITE, PLD_BRITE_MMGPIO_BASE },
+ { PLD_LCDEN, PLD_LCDEN_MMGPIO_BASE },
+ { PLD_TCH, PLD_TCH_MMGPIO_BASE },
+ { PLD_GPIO, PLD_GPIO_MMGPIO_BASE },
+};
+
static struct resource p720t_nand_resource[] __initdata = {
DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
};
@@ -92,11 +266,15 @@ static struct platform_device p720t_nand_pdev __initdata = {
static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
{
if (power) {
- PLD_LCDEN = PLD_LCDEN_EN;
- PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON;
+ gpio_set_value(PLD_LCDEN_EN, 1);
+ gpio_set_value(PLD_S1_ON, 1);
+ gpio_set_value(PLD_S2_ON, 1);
+ gpio_set_value(PLD_S4_ON, 1);
} else {
- PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON);
- PLD_LCDEN = 0;
+ gpio_set_value(PLD_S1_ON, 0);
+ gpio_set_value(PLD_S2_ON, 0);
+ gpio_set_value(PLD_S4_ON, 0);
+ gpio_set_value(PLD_LCDEN_EN, 0);
}
}
@@ -106,10 +284,7 @@ static struct plat_lcd_data p720t_lcd_power_pdata = {
static void p720t_lcd_backlight_set_intensity(int intensity)
{
- if (intensity)
- PLD_PWR |= PLD_S3_ON;
- else
- PLD_PWR = 0;
+ gpio_set_value(PLD_S3_ON, intensity);
}
static struct generic_bl_info p720t_lcd_backlight_pdata = {
@@ -119,19 +294,6 @@ static struct generic_bl_info p720t_lcd_backlight_pdata = {
.set_bl_intensity = p720t_lcd_backlight_set_intensity,
};
-/*
- * Map the P720T system PLD. It occupies two address spaces:
- * 0x10000000 and 0x10400000. We map both regions as one.
- */
-static struct map_desc p720t_io_desc[] __initdata = {
- {
- .virtual = SYSPLD_VIRT_BASE,
- .pfn = __phys_to_pfn(SYSPLD_PHYS_BASE),
- .length = SZ_8M,
- .type = MT_DEVICE,
- },
-};
-
static void __init
fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
{
@@ -157,33 +319,6 @@ fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
}
}
-static void __init p720t_map_io(void)
-{
- clps711x_map_io();
- iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
-}
-
-static void __init p720t_init_early(void)
-{
- /*
- * Power down as much as possible in case we don't
- * have the drivers loaded.
- */
- PLD_LCDEN = 0;
- PLD_PWR &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
-
- PLD_KBD = 0;
- PLD_IO = 0;
- PLD_IRDA = 0;
- PLD_CODEC = 0;
- PLD_TCH = 0;
- PLD_SPI = 0;
- if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
- PLD_COM2 = 0;
- PLD_COM1 = 0;
- }
-}
-
static struct gpio_led p720t_gpio_leds[] = {
{
.name = "User LED",
@@ -199,7 +334,20 @@ static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
static void __init p720t_init(void)
{
+ int i;
+
+ clps711x_devices_init();
+
+ for (i = 0; i < ARRAY_SIZE(mmgpios); i++)
+ p720t_mmgpio_init(mmgpios[i].addrbase, mmgpios[i].gpiobase);
+
platform_device_register(&p720t_nand_pdev);
+}
+
+static void __init p720t_init_late(void)
+{
+ WARN_ON(gpio_request_array(p720t_gpios, ARRAY_SIZE(p720t_gpios)));
+
platform_device_register_data(&platform_bus, "platform-lcd", 0,
&p720t_lcd_power_pdata,
sizeof(p720t_lcd_power_pdata));
@@ -207,10 +355,6 @@ static void __init p720t_init(void)
&p720t_lcd_backlight_pdata,
sizeof(p720t_lcd_backlight_pdata));
platform_device_register_simple("video-clps711x", 0, NULL, 0);
-}
-
-static void __init p720t_init_late(void)
-{
platform_device_register_data(&platform_bus, "leds-gpio", 0,
&p720t_gpio_led_pdata,
sizeof(p720t_gpio_led_pdata));
@@ -221,8 +365,8 @@ MACHINE_START(P720T, "ARM-Prospector720T")
.atag_offset = 0x100,
.nr_irqs = CLPS711X_NR_IRQS,
.fixup = fixup_p720t,
- .map_io = p720t_map_io,
- .init_early = p720t_init_early,
+ .map_io = clps711x_map_io,
+ .init_early = clps711x_init_early,
.init_irq = clps711x_init_irq,
.init_time = clps711x_timer_init,
.init_machine = p720t_init,
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f3ccf0..f6d1746366d4 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -27,12 +27,14 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clockchips.h>
+#include <linux/clocksource.h>
#include <linux/clk-provider.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
+#include <asm/sched_clock.h>
#include <asm/system_misc.h>
#include <mach/hardware.h>
@@ -213,7 +215,7 @@ void __init clps711x_init_irq(void)
}
}
-inline u32 fls16(u32 x)
+static inline u32 fls16(u32 x)
{
u32 r = 15;
@@ -237,27 +239,52 @@ inline u32 fls16(u32 x)
asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
{
- u32 irqstat;
- void __iomem *base = CLPS711X_VIRT_BASE;
-
- irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1);
- if (irqstat) {
- handle_IRQ(fls16(irqstat), regs);
- return;
- }
+ do {
+ u32 irqstat;
+ void __iomem *base = CLPS711X_VIRT_BASE;
+
+ irqstat = readw_relaxed(base + INTSR1) &
+ readw_relaxed(base + INTMR1);
+ if (irqstat)
+ handle_IRQ(fls16(irqstat), regs);
+
+ irqstat = readw_relaxed(base + INTSR2) &
+ readw_relaxed(base + INTMR2);
+ if (irqstat) {
+ handle_IRQ(fls16(irqstat) + 16, regs);
+ continue;
+ }
+
+ break;
+ } while (1);
+}
- irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2);
- if (likely(irqstat))
- handle_IRQ(fls16(irqstat) + 16, regs);
+static u32 notrace clps711x_sched_clock_read(void)
+{
+ return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
}
static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
+ disable_irq(IRQ_TC2OI);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ enable_irq(IRQ_TC2OI);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ /* Not supported */
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_RESUME:
+ /* Left event sources disabled, no more interrupts appear */
+ break;
+ }
}
static struct clock_event_device clockevent_clps711x = {
- .name = "CLPS711x Clockevents",
+ .name = "clps711x-clockevent",
.rating = 300,
.features = CLOCK_EVT_FEAT_PERIODIC,
.set_mode = clps711x_clockevent_set_mode,
@@ -271,8 +298,8 @@ static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
}
static struct irqaction clps711x_timer_irq = {
- .name = "CLPS711x Timer Tick",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .name = "clps711x-timer",
+ .flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = clps711x_timer_interrupt,
};
@@ -301,6 +328,7 @@ void __init clps711x_timer_init(void)
cpu = ext;
bus = cpu;
spi = 135400;
+ pll = 0;
} else {
cpu = pll;
if (cpu >= 36864000)
@@ -319,9 +347,9 @@ void __init clps711x_timer_init(void)
else
timh = 541440;
} else
- timh = cpu / 144;
+ timh = DIV_ROUND_CLOSEST(cpu, 144);
- timl = timh / 256;
+ timl = DIV_ROUND_CLOSEST(timh, 256);
/* All clocks are fixed */
add_fixed_clk(clk_pll, "pll", pll);
@@ -334,13 +362,24 @@ void __init clps711x_timer_init(void)
pr_info("CPU frequency set at %i Hz.\n", cpu);
+ /* Start Timer1 in free running mode (Low frequency) */
+ tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
+ clps_writel(tmp, SYSCON1);
+
+ setup_sched_clock(clps711x_sched_clock_read, 16, timl);
+
+ clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
+ "clps711x_clocksource", timl, 300, 16,
+ clocksource_mmio_readw_down);
+
+ /* Set Timer2 prescaler */
clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
- tmp = clps_readl(SYSCON1);
- tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
+ /* Start Timer2 in prescale mode (High frequency)*/
+ tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
clps_writel(tmp, SYSCON1);
- clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
+ clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
}
@@ -353,15 +392,11 @@ void clps711x_restart(char mode, const char *cmd)
static void clps711x_idle(void)
{
clps_writel(1, HALT);
- __asm__ __volatile__(
- "mov r0, r0\n\
- mov r0, r0");
+ asm("mov r0, r0");
+ asm("mov r0, r0");
}
-static int __init clps711x_idle_init(void)
+void __init clps711x_init_early(void)
{
arm_pm_idle = clps711x_idle;
- return 0;
}
-
-arch_initcall(clps711x_idle_init);
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a7292c70e..2a22f4c6cc75 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -13,3 +13,4 @@ extern void clps711x_init_irq(void);
extern void clps711x_timer_init(void);
extern void clps711x_handle_irq(struct pt_regs *regs);
extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_init_early(void);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
new file mode 100644
index 000000000000..856b81cf2f8a
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.c
@@ -0,0 +1,68 @@
+/*
+ * CLPS711X common devices definitions
+ *
+ * Author: Alexander Shiyan <shc_work@mail.ru>, 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/sizes.h>
+
+#include <mach/hardware.h>
+
+static const phys_addr_t clps711x_gpios[][2] __initconst = {
+ { PADR, PADDR },
+ { PBDR, PBDDR },
+ { PCDR, PCDDR },
+ { PDDR, PDDDR },
+ { PEDR, PEDDR },
+};
+
+static void __init clps711x_add_gpio(void)
+{
+ unsigned i;
+ struct resource gpio_res[2];
+
+ memset(gpio_res, 0, sizeof(gpio_res));
+
+ gpio_res[0].flags = IORESOURCE_MEM;
+ gpio_res[1].flags = IORESOURCE_MEM;
+
+ for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) {
+ gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0];
+ gpio_res[0].end = gpio_res[0].start;
+ gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1];
+ gpio_res[1].end = gpio_res[1].start;
+
+ platform_device_register_simple("clps711x-gpio", i,
+ gpio_res, ARRAY_SIZE(gpio_res));
+ }
+}
+
+const struct resource clps711x_syscon_res[] __initconst = {
+ /* SYSCON1, SYSFLG1 */
+ DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128),
+ /* SYSCON2, SYSFLG2 */
+ DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128),
+ /* SYSCON3 */
+ DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64),
+};
+
+static void __init clps711x_add_syscon(void)
+{
+ unsigned i;
+
+ for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++)
+ platform_device_register_simple("clps711x-syscon", i + 1,
+ &clps711x_syscon_res[i], 1);
+}
+
+void __init clps711x_devices_init(void)
+{
+ clps711x_add_gpio();
+ clps711x_add_syscon();
+}
diff --git a/arch/arm/mach-clps711x/devices.h b/arch/arm/mach-clps711x/devices.h
new file mode 100644
index 000000000000..a5efc1744b84
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.h
@@ -0,0 +1,12 @@
+/*
+ * CLPS711X common devices definitions
+ *
+ * Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+void clps711x_devices_init(void);
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
deleted file mode 100644
index 0452f5f3f034..000000000000
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * AUTCPU12 specific defines
- *
- * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_AUTCPU12_H
-#define __ASM_ARCH_AUTCPU12_H
-
-/*
- * The flash bank is wired to chip select 0
- */
-#define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */
-
-/* offset for device specific information structure */
-#define AUTCPU12_LCDINFO_OFFS (0x00010000)
-
-/* Videomemory in the internal SRAM (CS 6) */
-#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE
-
-/*
-* All special IO's are tied to CS1
-*/
-#define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */
-
-#define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */
-
-#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */
-
-#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */
-
-#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */
-
-#define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */
-
-#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */
-
-/*
-* defines for lcd contrast
-*/
-#define AUTCPU12_DPOT_PORT_OFFSET PEDR
-#define AUTCPU12_DPOT_CS (1<<0)
-#define AUTCPU12_DPOT_CLK (1<<1)
-#define AUTCPU12_DPOT_UD (1<<2)
-
-#endif
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 01d1b9559710..0286f4bf9945 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -21,6 +21,8 @@
#ifndef __MACH_CLPS711X_H
#define __MACH_CLPS711X_H
+#include <linux/mfd/syscon/clps711x.h>
+
#define CLPS711X_PHYS_BASE (0x80000000)
#define PADR (0x0000)
@@ -96,83 +98,9 @@
#define RANDID2 (0x2708)
#define RANDID3 (0x270c)
-/* common bits: SYSCON1 / SYSCON2 */
-#define SYSCON_UARTEN (1 << 8)
-
-#define SYSCON1_KBDSCAN(x) ((x) & 15)
-#define SYSCON1_KBDSCANMASK (15)
-#define SYSCON1_TC1M (1 << 4)
-#define SYSCON1_TC1S (1 << 5)
-#define SYSCON1_TC2M (1 << 6)
-#define SYSCON1_TC2S (1 << 7)
-#define SYSCON1_UART1EN SYSCON_UARTEN
-#define SYSCON1_BZTOG (1 << 9)
-#define SYSCON1_BZMOD (1 << 10)
-#define SYSCON1_DBGEN (1 << 11)
-#define SYSCON1_LCDEN (1 << 12)
-#define SYSCON1_CDENTX (1 << 13)
-#define SYSCON1_CDENRX (1 << 14)
-#define SYSCON1_SIREN (1 << 15)
-#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
-#define SYSCON1_ADCKSEL_MASK (3 << 16)
-#define SYSCON1_EXCKEN (1 << 18)
-#define SYSCON1_WAKEDIS (1 << 19)
-#define SYSCON1_IRTXM (1 << 20)
-
-/* common bits: SYSFLG1 / SYSFLG2 */
-#define SYSFLG_UBUSY (1 << 11)
-#define SYSFLG_URXFE (1 << 22)
-#define SYSFLG_UTXFF (1 << 23)
-
-#define SYSFLG1_MCDR (1 << 0)
-#define SYSFLG1_DCDET (1 << 1)
-#define SYSFLG1_WUDR (1 << 2)
-#define SYSFLG1_WUON (1 << 3)
-#define SYSFLG1_CTS (1 << 8)
-#define SYSFLG1_DSR (1 << 9)
-#define SYSFLG1_DCD (1 << 10)
-#define SYSFLG1_UBUSY SYSFLG_UBUSY
-#define SYSFLG1_NBFLG (1 << 12)
-#define SYSFLG1_RSTFLG (1 << 13)
-#define SYSFLG1_PFFLG (1 << 14)
-#define SYSFLG1_CLDFLG (1 << 15)
-#define SYSFLG1_URXFE SYSFLG_URXFE
-#define SYSFLG1_UTXFF SYSFLG_UTXFF
-#define SYSFLG1_CRXFE (1 << 24)
-#define SYSFLG1_CTXFF (1 << 25)
-#define SYSFLG1_SSIBUSY (1 << 26)
-#define SYSFLG1_ID (1 << 29)
-#define SYSFLG1_VERID(x) (((x) >> 30) & 3)
-#define SYSFLG1_VERID_MASK (3 << 30)
-
-#define SYSFLG2_SSRXOF (1 << 0)
-#define SYSFLG2_RESVAL (1 << 1)
-#define SYSFLG2_RESFRM (1 << 2)
-#define SYSFLG2_SS2RXFE (1 << 3)
-#define SYSFLG2_SS2TXFF (1 << 4)
-#define SYSFLG2_SS2TXUF (1 << 5)
-#define SYSFLG2_CKMODE (1 << 6)
-#define SYSFLG2_UBUSY SYSFLG_UBUSY
-#define SYSFLG2_URXFE SYSFLG_URXFE
-#define SYSFLG2_UTXFF SYSFLG_UTXFF
-
#define LCDCON_GSEN (1 << 30)
#define LCDCON_GSMD (1 << 31)
-#define SYSCON2_SERSEL (1 << 0)
-#define SYSCON2_KBD6 (1 << 1)
-#define SYSCON2_DRAMZ (1 << 2)
-#define SYSCON2_KBWEN (1 << 3)
-#define SYSCON2_SS2TXEN (1 << 4)
-#define SYSCON2_PCCARD1 (1 << 5)
-#define SYSCON2_PCCARD2 (1 << 6)
-#define SYSCON2_SS2RXEN (1 << 7)
-#define SYSCON2_UART2EN SYSCON_UARTEN
-#define SYSCON2_SS2MAEN (1 << 9)
-#define SYSCON2_OSTB (1 << 12)
-#define SYSCON2_CLKENSL (1 << 13)
-#define SYSCON2_BUZFREQ (1 << 14)
-
/* common bits: UARTDR1 / UARTDR2 */
#define UARTDR_FRMERR (1 << 8)
#define UARTDR_PARERR (1 << 9)
@@ -228,18 +156,6 @@
#define DAI64FS_MCLK256EN (1 << 3)
#define DAI64FS_LOOPBACK (1 << 5)
-#define SYSCON3_ADCCON (1 << 0)
-#define SYSCON3_CLKCTL0 (1 << 1)
-#define SYSCON3_CLKCTL1 (1 << 2)
-#define SYSCON3_DAISEL (1 << 3)
-#define SYSCON3_ADCCKNSEN (1 << 4)
-#define SYSCON3_VERSN(x) (((x) >> 5) & 7)
-#define SYSCON3_VERSN_MASK (7 << 5)
-#define SYSCON3_FASTWAKE (1 << 8)
-#define SYSCON3_DAIEN (1 << 9)
-#define SYSCON3_128FS SYSCON3_DAIEN
-#define SYSCON3_ENPD67 (1 << 10)
-
#define SDCONF_ACTIVE (1 << 10)
#define SDCONF_CLKCTL (1 << 9)
#define SDCONF_WIDTH_4 (0 << 7)
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 2f23dd5d73e4..c5a8ea6839ef 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -70,11 +70,4 @@
#define CLPS711X_SDRAM0_BASE (0xc0000000)
#define CLPS711X_SDRAM1_BASE (0xd0000000)
-#if defined (CONFIG_ARCH_EDB7211)
-
-/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
-#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE
-
-#endif /* CONFIG_ARCH_EDB7211 */
-
#endif
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
deleted file mode 100644
index fc0e028d9405..000000000000
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-clps711x/include/mach/memory.h
- *
- * Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PLAT_PHYS_OFFSET UL(0xc0000000)
-
-/*
- * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
- * uses only one of the two banks (bank #1). However, even within
- * bank #1, memory is discontiguous.
- *
- * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
- * them, so we use 24 for the node max shift to get 16MB node sizes.
- */
-
-#define SECTION_SIZE_BITS 24
-#define MAX_PHYSMEM_BITS 32
-
-#endif
-
diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h
deleted file mode 100644
index 9a433155bf58..000000000000
--- a/arch/arm/mach-clps711x/include/mach/syspld.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-clps711x/include/mach/syspld.h
- *
- * System Control PLD register definitions.
- *
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_SYSPLD_H
-#define __ASM_ARCH_SYSPLD_H
-
-#define SYSPLD_PHYS_BASE (0x10000000)
-#define SYSPLD_VIRT_BASE IO_ADDRESS(SYSPLD_PHYS_BASE)
-
-#define SYSPLD_REG(type, off) (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
-
-#define PLD_INT SYSPLD_REG(u32, 0x000000)
-#define PLD_INT_PENIRQ (1 << 5)
-#define PLD_INT_UCB_IRQ (1 << 1)
-#define PLD_INT_KBD_ATN (1 << 0) /* EINT1 */
-
-#define PLD_PWR SYSPLD_REG(u32, 0x000004)
-#define PLD_PWR_EXT (1 << 5)
-#define PLD_PWR_MODE (1 << 4) /* 1 = PWM, 0 = PFM */
-#define PLD_S4_ON (1 << 3) /* LCD bias voltage enable */
-#define PLD_S3_ON (1 << 2) /* LCD backlight enable */
-#define PLD_S2_ON (1 << 1) /* LCD 3V3 supply enable */
-#define PLD_S1_ON (1 << 0) /* LCD 3V supply enable */
-
-#define PLD_KBD SYSPLD_REG(u32, 0x000008)
-#define PLD_KBD_WAKE (1 << 1)
-#define PLD_KBD_EN (1 << 0)
-
-#define PLD_SPI SYSPLD_REG(u32, 0x00000c)
-#define PLD_SPI_EN (1 << 0)
-
-#define PLD_IO SYSPLD_REG(u32, 0x000010)
-#define PLD_IO_BOOTSEL (1 << 6) /* boot sel switch */
-#define PLD_IO_USER (1 << 5) /* user defined switch */
-#define PLD_IO_LED3 (1 << 4)
-#define PLD_IO_LED2 (1 << 3)
-#define PLD_IO_LED1 (1 << 2)
-#define PLD_IO_LED0 (1 << 1)
-#define PLD_IO_LEDEN (1 << 0)
-
-#define PLD_IRDA SYSPLD_REG(u32, 0x000014)
-#define PLD_IRDA_EN (1 << 0)
-
-#define PLD_COM2 SYSPLD_REG(u32, 0x000018)
-#define PLD_COM2_EN (1 << 0)
-
-#define PLD_COM1 SYSPLD_REG(u32, 0x00001c)
-#define PLD_COM1_EN (1 << 0)
-
-#define PLD_AUD SYSPLD_REG(u32, 0x000020)
-#define PLD_AUD_DIV1 (1 << 6)
-#define PLD_AUD_DIV0 (1 << 5)
-#define PLD_AUD_CLK_SEL1 (1 << 4)
-#define PLD_AUD_CLK_SEL0 (1 << 3)
-#define PLD_AUD_MIC_PWR (1 << 2)
-#define PLD_AUD_MIC_GAIN (1 << 1)
-#define PLD_AUD_CODEC_EN (1 << 0)
-
-#define PLD_CF SYSPLD_REG(u32, 0x000024)
-#define PLD_CF2_SLEEP (1 << 5)
-#define PLD_CF1_SLEEP (1 << 4)
-#define PLD_CF2_nPDREQ (1 << 3)
-#define PLD_CF1_nPDREQ (1 << 2)
-#define PLD_CF2_nIRQ (1 << 1)
-#define PLD_CF1_nIRQ (1 << 0)
-
-#define PLD_SDC SYSPLD_REG(u32, 0x000028)
-#define PLD_SDC_INT_EN (1 << 2)
-#define PLD_SDC_WP (1 << 1)
-#define PLD_SDC_CD (1 << 0)
-
-#define PLD_FPGA SYSPLD_REG(u32, 0x00002c)
-
-#define PLD_CODEC SYSPLD_REG(u32, 0x400000)
-#define PLD_CODEC_IRQ3 (1 << 4)
-#define PLD_CODEC_IRQ2 (1 << 3)
-#define PLD_CODEC_IRQ1 (1 << 2)
-#define PLD_CODEC_EN (1 << 0)
-
-#define PLD_BRITE SYSPLD_REG(u32, 0x400004)
-#define PLD_BRITE_UP (1 << 1)
-#define PLD_BRITE_DN (1 << 0)
-
-#define PLD_LCDEN SYSPLD_REG(u32, 0x400008)
-#define PLD_LCDEN_EN (1 << 0)
-
-#define PLD_ID SYSPLD_REG(u32, 0x40000c)
-
-#define PLD_TCH SYSPLD_REG(u32, 0x400010)
-#define PLD_TCH_PENIRQ (1 << 1)
-#define PLD_TCH_EN (1 << 0)
-
-#define PLD_GPIO SYSPLD_REG(u32, 0x400014)
-#define PLD_GPIO2 (1 << 2)
-#define PLD_GPIO1 (1 << 1)
-#define PLD_GPIO0 (1 << 0)
-
-#endif