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authorKevin Hilman <khilman@linaro.org>2013-08-14 08:14:50 -0700
committerKevin Hilman <khilman@linaro.org>2013-08-14 08:14:50 -0700
commit080e3da4f4bf693ec59bd98eae3ee5bd5b1dd047 (patch)
tree2a367e97dcffe9ced54ff71b03ab893a3248fdb4 /arch/arm/kernel/head.S
parente91f24ae027a583f2faff84456fa2630144bfed8 (diff)
parent39c41df9c1950fba0ee6a4e7a63be281e89fe437 (diff)
downloadlwn-080e3da4f4bf693ec59bd98eae3ee5bd5b1dd047.tar.gz
lwn-080e3da4f4bf693ec59bd98eae3ee5bd5b1dd047.zip
Merge branch 'zynq/dt' into next/dt
* zynq/dt: (1054 commits) arm: zynq: dt: Set correct L2 ram latencies + v3.11-rc5 Conflicts: arch/arm/Makefile
Diffstat (limited to 'arch/arm/kernel/head.S')
-rw-r--r--arch/arm/kernel/head.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 45e8935cae4e..2c7cc1e03473 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -343,7 +343,7 @@ __turn_mmu_on_loc:
.long __turn_mmu_on_end
#if defined(CONFIG_SMP)
- __CPUINIT
+ .text
ENTRY(secondary_startup)
/*
* Common entry point for secondary CPUs.