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| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-21 10:00:22 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-21 10:00:22 -0700 |
| commit | d07b3c25327c5ae3792d0ed0c135dee4727200a1 (patch) | |
| tree | 2ffad8da1f9004bdeb32bf76faa08fa104797b89 /arch/arm/common/gic.c | |
| parent | dde33348e53ecab687a9768bf5262f0b8f79b7f2 (diff) | |
| parent | 6cbdc8c5357276307a77deeada3f04626ff17da6 (diff) | |
| download | lwn-d07b3c25327c5ae3792d0ed0c135dee4727200a1.tar.gz lwn-d07b3c25327c5ae3792d0ed0c135dee4727200a1.zip | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits)
[ARM] spelling fixes
[ARM] at91_adc parenthesis balance
[ARM] 4400/1: S3C24XX: Add high-speed MMC device definition
[ARM] 4399/2: S3C2443: Fix SMDK2443 nand timings
[ARM] 4398/1: S3C2443: Fix watchdog IRQ number
[ARM] 4397/1: S3C2443: remove SDI0/1 IRQ ambiguity
[ARM] 4396/1: S3C2443: Add missing HCLK clocks
[ARM] 4395/1: S3C24XX: add include of <linux/sysdev.h> to relevant machines
[ARM] 4388/1: no need for arm/mm mmap range checks for non-mmu
[ARM] 4387/1: fix /proc/cpuinfo formatting for pre-ARM7 parts
[ARM] ARMv6: add CPU_HAS_ASID configuration
[ARM] integrator: fix pci_v3 compile error with DEBUG_LL
[ARM] gic: Fix gic cascade irq handling
[ARM] Silence OMAP kernel configuration warning
[ARM] Update ARM syscalls
[ARM] 4384/1: S3C2412/13 SPI registers offset correction
[ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files
[ARM] 4382/1: iop13xx: fix msi support
[ARM] Remove Integrator/CP SMP platform support
[ARM] 4378/1: KS8695: Serial driver fix
...
Diffstat (limited to 'arch/arm/common/gic.c')
| -rw-r--r-- | arch/arm/common/gic.c | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 4deece5fbdf4..0c89bd35e06f 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -72,7 +72,7 @@ static inline unsigned int gic_irq(unsigned int irq) * unmask it, in the same way we need to unmask an interrupt when * we first enable it. * - * The GIC has a seperate notion of "end of interrupt" to re-enable + * The GIC has a separate notion of "end of interrupt" to re-enable * an interrupt after handling, in order to support hardware * prioritisation. * @@ -125,12 +125,11 @@ static void gic_set_cpu(unsigned int irq, cpumask_t mask_val) } #endif -static void fastcall gic_handle_cascade_irq(unsigned int irq, - struct irq_desc *desc) +static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { struct gic_chip_data *chip_data = get_irq_data(irq); struct irq_chip *chip = get_irq_chip(irq); - unsigned int cascade_irq; + unsigned int cascade_irq, gic_irq; unsigned long status; /* primary controller ack'ing */ @@ -140,16 +139,15 @@ static void fastcall gic_handle_cascade_irq(unsigned int irq, status = readl(chip_data->cpu_base + GIC_CPU_INTACK); spin_unlock(&irq_controller_lock); - cascade_irq = (status & 0x3ff); - if (cascade_irq > 1020) + gic_irq = (status & 0x3ff); + if (gic_irq == 1023) goto out; - if (cascade_irq < 32 || cascade_irq >= NR_IRQS) { - do_bad_IRQ(cascade_irq, desc); - goto out; - } - cascade_irq += chip_data->irq_offset; - generic_handle_irq(cascade_irq); + cascade_irq = gic_irq + chip_data->irq_offset; + if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) + do_bad_IRQ(cascade_irq, desc); + else + generic_handle_irq(cascade_irq); out: /* primary controller unmasking */ |