diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-06 17:40:41 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-07 07:45:12 +0100 |
| commit | a0504f0880c11da301dc2b5a5135bd02376e367e (patch) | |
| tree | a00ac8116bf946bf5b2f5bd9200d2e1cc58c45b7 /arch/arm/boot/dts/r8a7792.dtsi | |
| parent | 5d6a2165abd4635ecf5ece3d02fe8677f00d32c5 (diff) | |
| download | lwn-a0504f0880c11da301dc2b5a5135bd02376e367e.tar.gz lwn-a0504f0880c11da301dc2b5a5135bd02376e367e.zip | |
ARM: dts: r8a7792: Remove unit-address and reg from integrated cache
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 8ecfda7a004e..c762f44f7732 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -60,9 +60,8 @@ next-level-cache = <&L2_CA15>; }; - L2_CA15: cache-controller@0 { + L2_CA15: cache-controller-0 { compatible = "cache"; - reg = <0>; cache-unified; cache-level = <2>; power-domains = <&sysc R8A7792_PD_CA15_SCU>; |