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| author | Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> | 2021-11-04 03:22:30 -0700 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2021-11-04 19:48:47 +0100 |
| commit | 074d0cdfbb2f5985c5748fe80f6f8a2a7db8b63f (patch) | |
| tree | 8c5ed1eeea9150ec9d3488d477f9d200d55e04c4 /Documentation | |
| parent | 5521055670a53bd495676d1163b40ecb0a37af9c (diff) | |
| download | lwn-074d0cdfbb2f5985c5748fe80f6f8a2a7db8b63f.tar.gz lwn-074d0cdfbb2f5985c5748fe80f6f8a2a7db8b63f.zip | |
cpufreq: intel_pstate: Clear HWP Status during HWP Interrupt enable
It is possible that some performance excursions happened before OS boot
or enable HWP interrupts. So clear MSR_HWP_STATUS bits when we enable
HWP interrupt. In this way a next excursion will results in a HWP
interrupt.
The status bits of MSR_HWP_STATUS must be cleared (0) by software so
that a new status condition change will cause the hardware to set the
bit again and issue the notification.
Fixes: 57577c996d73 ("cpufreq: intel_pstate: Process HWP Guaranteed change notification")
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions