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authorJoerg Roedel <joerg.roedel@amd.com>2008-09-18 15:23:43 +0200
committerIngo Molnar <mingo@elte.hu>2008-09-19 12:59:06 +0200
commit2842e5bf3115193f05dc9dac20f940e7abf44c1a (patch)
tree31461a4fb45db1868f4bfb9f99251db7a5ce6d33 /Documentation/kernel-parameters.txt
parent270cab2426cdc6307725e4f1f46ecf8ab8e69193 (diff)
downloadlwn-2842e5bf3115193f05dc9dac20f940e7abf44c1a.tar.gz
lwn-2842e5bf3115193f05dc9dac20f940e7abf44c1a.zip
x86: move GART TLB flushing options to generic code
The GART currently implements the iommu=[no]fullflush command line parameters which influence its IO/TLB flushing strategy. This patch makes these parameters generic so that they can be used by the AMD IOMMU too. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'Documentation/kernel-parameters.txt')
-rw-r--r--Documentation/kernel-parameters.txt4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 1150444a21ab..40066ceb48fe 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -893,6 +893,10 @@ and is between 256 and 4096 characters. It is defined in the file
nomerge
forcesac
soft
+ fullflush
+ Flush IO/TLB at every deallocation
+ nofullflush
+ Flush IO/TLB only when addresses are reused (default)
intel_iommu= [DMAR] Intel IOMMU driver (DMAR) option