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authorConor Dooley <conor.dooley@microchip.com>2022-06-29 19:43:33 +0100
committerMark Brown <broonie@kernel.org>2022-07-01 10:05:04 +0100
commit8b037cabc4966b010c44a76e05a43d276318bc49 (patch)
tree0a8ec755f12c358e262c1a7b69f707e2d2ca5d56 /Documentation/devicetree/bindings/spi
parent10365cad180273dee6c5e3b3e29f951ca8e92b53 (diff)
downloadlwn-8b037cabc4966b010c44a76e05a43d276318bc49.tar.gz
lwn-8b037cabc4966b010c44a76e05a43d276318bc49.zip
spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width
Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the Canaan k210 is wired up for a width of 4. Quoting Serge: The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. /endquote As such, drop the restriction on only supporting a bus width of 1. Link: https://lore.kernel.org/all/20220620205654.g7fyipwytbww5757@mobilestation/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Niklas Cassel <niklas.cassel@wdc.com> Link: https://lore.kernel.org/r/20220629184343.3438856-5-mail@conchuod.ie Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
-rw-r--r--Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml6
1 files changed, 0 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index e25d44c218f2..0a43d6e0ef91 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -143,12 +143,6 @@ patternProperties:
minimum: 0
maximum: 3
- spi-rx-bus-width:
- const: 1
-
- spi-tx-bus-width:
- const: 1
-
unevaluatedProperties: false
required: