diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-05 14:19:54 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-05 14:19:54 -0700 |
| commit | ff050ad12c551233e546506409c89eb2f640d9f3 (patch) | |
| tree | 8ae29fece122a91cbd6160fb2ca34c0ea82c3df9 | |
| parent | dfc25e4503aef6b82a1de4a0fbe19aafa8648fbe (diff) | |
| parent | 9233087dc468f75bdeb7830c694c09dc74be88c4 (diff) | |
| download | lwn-ff050ad12c551233e546506409c89eb2f640d9f3.tar.gz lwn-ff050ad12c551233e546506409c89eb2f640d9f3.zip | |
Merge tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC specific changes from Arnd Bergmann:
"Lots of changes specific to one of the SoC families. Some that stick
out are:
- mach-qcom gains new features, most importantly SMP support for the
newer chips (Stephen Boyd, Rohit Vaswani)
- mvebu gains support for three new SoCs: Armada 375, 380 and 385
(Thomas Petazzoni and Free-electrons team)
- SMP support for Rockchips (Heiko Stübner)
- Lots of i.MX changes (Shawn Guo)
- Added support for BCM5301x SoC (Hauke Mehrtens)
- Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn
and Sebastian Hesselbarth doing the final part of a long journey)
- Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd
Bergmann)"
* tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits)
ARM: sunxi: Select HAVE_ARM_ARCH_TIMER
ARM: cache-tauros2: remove ARMv6 code
ARM: mvebu: don't select CONFIG_NEON
ARM: davinci: fix DT booting with default defconfig
ARM: configs: bcm_defconfig: enable bcm590xx regulator support
ARM: davinci: remove tnetv107x support
MAINTAINERS: Update ARM STi maintainers
ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE
ARM: bcm21664: Add board support.
ARM: sunxi: Add the new watchog compatibles to the reboot code
ARM: enable ARM_HAS_SG_CHAIN for multiplatform
ARM: davinci: remove da8xx_omapl_defconfig
ARM: davinci: da8xx: fix multiple watchdog device registration
ARM: davinci: add da8xx specific configs to davinci_all_defconfig
ARM: davinci: enable da8xx build concurrently with older devices
ARM: BCM5301X: workaround suppress fault
ARM: BCM5301X: add early debugging support
ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU
ARM: mach-bcm: Remove GENERIC_TIME
ARM: shmobile: APMU: Fix warnings due to improper printk formats
...
172 files changed, 3918 insertions, 3679 deletions
diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index 5a930c1528ad..963ec445e15a 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README @@ -83,14 +83,24 @@ EBU Armada family 88F6710 88F6707 88F6W11 + Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf + + Armada 375 Flavors: + 88F6720 + Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA_375_SoC-01_product_brief.pdf + + Armada 380/385 Flavors: + 88F6810 + 88F6820 + 88F6828 Armada XP Flavors: MV78230 MV78260 MV78460 NOTE: not to be confused with the non-SMP 78xx0 SoCs + Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf - Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf No public datasheet available. Core: Sheeva ARMv7 compatible diff --git a/Documentation/devicetree/bindings/arm/armada-375.txt b/Documentation/devicetree/bindings/arm/armada-375.txt new file mode 100644 index 000000000000..867d0b80cb8f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-375.txt @@ -0,0 +1,9 @@ +Marvell Armada 375 Platforms Device Tree Bindings +------------------------------------------------- + +Boards with a SoC of the Marvell Armada 375 family shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armada375" diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt new file mode 100644 index 000000000000..11f2330a6554 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-38x.txt @@ -0,0 +1,10 @@ +Marvell Armada 38x Platforms Device Tree Bindings +------------------------------------------------- + +Boards with a SoC of the Marvell Armada 38x family shall have the +following property: + +Required root node property: + + - compatible: must contain either "marvell,armada380" or + "marvell,armada385" depending on the variant of the SoC being used. diff --git a/Documentation/devicetree/bindings/arm/bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm4708.txt new file mode 100644 index 000000000000..6b0f49f6f499 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm4708.txt @@ -0,0 +1,8 @@ +Broadcom BCM4708 device tree bindings +------------------------------------------- + +Boards with the BCM4708 SoC shall have the following properties: + +Required root node property: + +compatible = "brcm,bcm4708"; diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 91304353eea4..333f4aea3029 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -180,7 +180,11 @@ nodes to be present and contain the properties described below. be one of: "spin-table" "psci" - # On ARM 32-bit systems this property is optional. + # On ARM 32-bit systems this property is optional and + can be one of: + "qcom,gcc-msm8660" + "qcom,kpss-acc-v1" + "qcom,kpss-acc-v2" - cpu-release-addr Usage: required for systems that have an "enable-method" @@ -191,6 +195,21 @@ nodes to be present and contain the properties described below. property identifying a 64-bit zero-initialised memory location. + - qcom,saw + Usage: required for systems that have an "enable-method" + property value of "qcom,kpss-acc-v1" or + "qcom,kpss-acc-v2" + Value type: <phandle> + Definition: Specifies the SAW[1] node associated with this CPU. + + - qcom,acc + Usage: required for systems that have an "enable-method" + property value of "qcom,kpss-acc-v1" or + "qcom,kpss-acc-v2" + Value type: <phandle> + Definition: Specifies the ACC[2] node associated with this CPU. + + Example 1 (dual-cluster big.LITTLE system 32-bit): cpus { @@ -382,3 +401,7 @@ cpus { cpu-release-addr = <0 0x20000000>; }; }; + +-- +[1] arm/msm/qcom,saw2.txt +[2] arm/msm/qcom,kpss-acc.txt diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt new file mode 100644 index 000000000000..0d244b999d10 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt @@ -0,0 +1,16 @@ +* Marvell Feroceon Cache + +Required properties: +- compatible : Should be either "marvell,feroceon-cache" or + "marvell,kirkwood-cache". + +Optional properties: +- reg : Address of the L2 cache control register. Mandatory for + "marvell,kirkwood-cache", not used by "marvell,feroceon-cache" + + +Example: + l2: l2-cache@20128 { + compatible = "marvell,kirkwood-cache"; + reg = <0x20128 0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt new file mode 100644 index 000000000000..1333db9acfee --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt @@ -0,0 +1,30 @@ +Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) + +The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. +There is one ACC register region per CPU within the KPSS remapped region as +well as an alias register region that remaps accesses to the ACC associated +with the CPU accessing the region. + +PROPERTIES + +- compatible: + Usage: required + Value type: <string> + Definition: should be one of: + "qcom,kpss-acc-v1" + "qcom,kpss-acc-v2" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the first element specifies the base address and size of + the register region. An optional second element specifies + the base address and size of the alias register region. + +Example: + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x02088000 0x1000>, + <0x02008000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt new file mode 100644 index 000000000000..1505fb8e131a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt @@ -0,0 +1,35 @@ +SPM AVS Wrapper 2 (SAW2) + +The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the +Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable +micro-controller that transitions a piece of hardware (like a processor or +subsystem) into and out of low power modes via a direct connection to +the PMIC. It can also be wired up to interact with other processors in the +system, notifying them when a low power state is entered or exited. + +PROPERTIES + +- compatible: + Usage: required + Value type: <string> + Definition: shall contain "qcom,saw2". A more specific value should be + one of: + "qcom,saw2-v1" + "qcom,saw2-v1.1" + "qcom,saw2-v2" + "qcom,saw2-v2.1" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the first element specifies the base address and size of + the register region. An optional second element specifies + the base address and size of the alias register region. + + +Example: + + regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt index 081c6a786c8a..d24ab2ebf8a7 100644 --- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt @@ -1,12 +1,13 @@ MVEBU System Controller ----------------------- -MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x) +MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x) Required properties: - compatible: one of: - "marvell,orion-system-controller" - "marvell,armada-370-xp-system-controller" + - "marvell,armada-375-system-controller" - reg: Should contain system controller registers location and length. Example: diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt new file mode 100644 index 000000000000..3ee9b428b2f7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt @@ -0,0 +1,16 @@ +Rockchip power-management-unit: +------------------------------- + +The pmu is used to turn off and on different power domains of the SoCs +This includes the power to the CPU cores. + +Required node properties: +- compatible value : = "rockchip,rk3066-pmu"; +- reg : physical base address and the size of the registers window + +Example: + + pmu@20004000 { + compatible = "rockchip,rk3066-pmu"; + reg = <0x20004000 0x100>; + }; diff --git a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt new file mode 100644 index 000000000000..d9416fb8db6f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt @@ -0,0 +1,30 @@ +Rockchip SRAM for smp bringup: +------------------------------ + +Rockchip's smp-capable SoCs use the first part of the sram for the bringup +of the cores. Once the core gets powered up it executes the code that is +residing at the very beginning of the sram. + +Therefore a reserved section sub-node has to be added to the mmio-sram +declaration. + +Required sub-node properties: +- compatible : should be "rockchip,rk3066-smp-sram" + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sram.txt + +Example: + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smp-sram@10080000 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x10080000 0x50>; + }; + }; diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt index 0fd76c405208..6630d842c7a3 100644 --- a/Documentation/devicetree/bindings/bus/imx-weim.txt +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt @@ -8,7 +8,12 @@ The actual devices are instantiated from the child nodes of a WEIM node. Required properties: - - compatible: Should be set to "fsl,<soc>-weim" + - compatible: Should contain one of the following: + "fsl,imx1-weim" + "fsl,imx27-weim" + "fsl,imx51-weim" + "fsl,imx50-weim" + "fsl,imx6q-weim" - reg: A resource specifier for the register space (see the example below) - clocks: the clock, see the example below. @@ -19,6 +24,26 @@ Required properties: <cs-number> 0 <physical address of mapping> <size> +Optional properties: + + - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of + devices, it should be the phandle to the system General + Purpose Register controller that contains WEIM CS GPR + register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] + should be set up as one of the following 4 possible + values depending on the CS space configuration. + + IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 + --------------------------------------------- + 05 128M 0M 0M 0M + 033 64M 64M 0M 0M + 0113 64M 32M 32M 0M + 01111 32M 32M 32M 32M + + In case that the property is absent, the reset value or + what bootloader sets up in IOMUXC_GPR1[11:0] will be + used. + Timing property for child nodes. It is mandatory, not optional. - fsl,weim-cs-timing: The timing array, contains timing values for the @@ -43,6 +68,7 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0x08000000 0x08000000>; + fsl,weim-cs-gpr = <&gpr>; nor@0,0 { compatible = "cfi-flash"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt new file mode 100644 index 000000000000..759339c34e4f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt @@ -0,0 +1,41 @@ +Cirrus Logic CLPS711X Interrupt Controller + +Required properties: + +- compatible: Should be "cirrus,clps711x-intc". +- reg: Specifies base physical address of the registers set. +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. + +The interrupt sources are as follows: +ID Name Description +--------------------------- +1: BLINT Battery low (FIQ) +3: MCINT Media changed (FIQ) +4: CSINT CODEC sound +5: EINT1 External 1 +6: EINT2 External 2 +7: EINT3 External 3 +8: TC1OI TC1 under flow +9: TC2OI TC2 under flow +10: RTCMI RTC compare match +11: TINT 64Hz tick +12: UTXINT1 UART1 transmit FIFO half empty +13: URXINT1 UART1 receive FIFO half full +14: UMSINT UART1 modem status changed +15: SSEOTI SSI1 end of transfer +16: KBDINT Keyboard +17: SS2RX SSI2 receive FIFO half or greater full +18: SS2TX SSI2 transmit FIFO less than half empty +28: UTXINT2 UART2 transmit FIFO half empty +29: URXINT2 UART2 receive FIFO half full +32: DAIINT DAI interface (FIQ) + +Example: + intc: interrupt-controller { + compatible = "cirrus,clps711x-intc"; + reg = <0x80000000 0x4000>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 74e33b8913bf..2421c8d5ec5c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1291,13 +1291,21 @@ S: Maintained F: drivers/clk/socfpga/ ARM/STI ARCHITECTURE -M: Srinivas Kandagatla <srinivas.kandagatla@st.com> -M: Stuart Menefy <stuart.menefy@st.com> +M: Srinivas Kandagatla <srinivas.kandagatla@gmail.com> +M: Maxime Coquelin <maxime.coquelin@st.com> +M: Patrice Chotard <patrice.chotard@st.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: kernel@stlinux.com W: http://www.stlinux.com S: Maintained F: arch/arm/mach-sti/ +F: arch/arm/boot/dts/sti* +F: drivers/clocksource/arm_global_timer.c +F: drivers/reset/sti/ +F: drivers/pinctrl/pinctrl-st.c +F: drivers/media/rc/st_rc.c +F: drivers/i2c/busses/i2c-st.c +F: drivers/tty/serial/st-asc.c ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT M: Lennert Buytenhek <kernel@wantstofly.org> @@ -1907,6 +1915,14 @@ F: arch/arm/boot/dts/bcm2835* F: arch/arm/configs/bcm2835_defconfig F: drivers/*/*bcm2835* +BROADCOM BCM5301X ARM ARCHICTURE +M: Hauke Mehrtens <hauke@hauke-m.de> +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: arch/arm/mach-bcm/bcm_5301x.c +F: arch/arm/boot/dts/bcm5301x.dtsi +F: arch/arm/boot/dts/bcm470* + BROADCOM TG3 GIGABIT ETHERNET DRIVER M: Nithin Nayak Sujir <nsujir@broadcom.com> M: Michael Chan <mchan@broadcom.com> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 83912d0251ca..b4935db86f37 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -310,6 +310,7 @@ config ARCH_MULTIPLATFORM bool "Allow multiple platforms to be selected" depends on MMU select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_HAS_SG_CHAIN select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR select COMMON_CLK @@ -393,8 +394,6 @@ config ARCH_CLPS711X select CPU_ARM720T select GENERIC_CLOCKEVENTS select MFD_SYSCON - select MULTI_IRQ_HANDLER - select SPARSE_IRQ help Support for Cirrus Logic 711x/721x/731x based boards. @@ -909,7 +908,7 @@ config ARCH_MULTI_V5 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" depends on !ARCH_MULTI_V6_V7 select ARCH_MULTI_V4_V5 - select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \ + select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 76ee27829c34..8983919a4421 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -106,9 +106,14 @@ choice depends on ARCH_BCM2835 select DEBUG_UART_PL01X + config DEBUG_BCM_5301X + bool "Kernel low-level debugging on BCM5301X UART1" + depends on ARCH_BCM_5301X + select DEBUG_UART_PL01X + config DEBUG_BCM_KONA_UART bool "Kernel low-level debugging messages via BCM KONA UART" - depends on ARCH_BCM + depends on ARCH_BCM_MOBILE select DEBUG_UART_8250 help Say Y here if you want kernel low-level debugging support @@ -171,15 +176,6 @@ choice Say Y here if you want the debug print routines to direct their output to UART0 serial port on DaVinci DMx devices. - config DEBUG_DAVINCI_TNETV107X_UART1 - bool "Kernel low-level debugging on DaVinci TNETV107x using UART1" - depends on ARCH_DAVINCI_TNETV107X - select DEBUG_UART_8250 - help - Say Y here if you want the debug print routines to direct - their output to UART1 serial port on DaVinci TNETV107X - devices. - config DEBUG_ZYNQ_UART0 bool "Kernel low-level debugging on Xilinx Zynq using UART0" depends on ARCH_ZYNQ @@ -1014,7 +1010,6 @@ config DEBUG_UART_PHYS default 0x02530c00 if DEBUG_KEYSTONE_UART0 default 0x02531000 if DEBUG_KEYSTONE_UART1 default 0x03010fe0 if ARCH_RPC - default 0x08108300 if DEBUG_DAVINCI_TNETV107X_UART1 default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \ DEBUG_VEXPRESS_UART0_CA9 default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT @@ -1023,6 +1018,7 @@ config DEBUG_UART_PHYS default 0x101f1000 if ARCH_VERSATILE default 0x101fb000 if DEBUG_NOMADIK_UART default 0x16000000 if ARCH_INTEGRATOR + default 0x18000300 if DEBUG_BCM_5301X default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1 default 0x20060000 if DEBUG_RK29_UART0 default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 @@ -1071,6 +1067,7 @@ config DEBUG_UART_VIRT default 0xf0009000 if DEBUG_CNS3XXX default 0xf01fb000 if DEBUG_NOMADIK_UART default 0xf0201000 if DEBUG_BCM2835 + default 0xf1000300 if DEBUG_BCM_5301X default 0xf11f1000 if ARCH_VERSATILE default 0xf1600000 if ARCH_INTEGRATOR default 0xf1c28000 if DEBUG_SUNXI_UART0 @@ -1110,7 +1107,6 @@ config DEBUG_UART_VIRT default 0xfed12000 if ARCH_KIRKWOOD default 0xfedc0000 if ARCH_EP93XX default 0xfee003f8 if FOOTBRIDGE - default 0xfee08300 if DEBUG_DAVINCI_TNETV107X_UART1 default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART default 0xfef36000 if DEBUG_HIGHBANK_UART default 0xfee82340 if ARCH_IOP13XX @@ -1135,7 +1131,7 @@ config DEBUG_UART_8250_WORD default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \ ARCH_KEYSTONE || \ DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ - DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \ + DEBUG_DAVINCI_DA8XX_UART2 || \ DEBUG_BCM_KONA_UART config DEBUG_UART_8250_FLOW_CONTROL diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ec4dd7c3ed37..112813a80b71 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -59,7 +59,7 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2cd-google-chromecast.dtb dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ da850-evm.dtb -dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ +dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ dove-cubox.dtb \ dove-d2plug.dtb \ dove-d3plug.dtb \ @@ -86,8 +86,8 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ integratorcp.dtb -dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb -dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ +kirkwood := \ + kirkwood-cloudbox.dtb \ kirkwood-db-88f6281.dtb \ kirkwood-db-88f6282.dtb \ kirkwood-dns320.dtb \ @@ -121,6 +121,9 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-topkick.dtb \ kirkwood-ts219-6281.dtb \ kirkwood-ts219-6282.dtb +dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood) +dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood) +dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index dc86429756d7..2cb0dc529165 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -122,4 +122,66 @@ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0>; + dsa,mii-bus = <ðphy0>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0>; /* MDIO address 0, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@ff { + reg = <0xff>; /* No phy attached */ + speed = <1000>; + duplex = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index ff002826552a..3a9c3caa9aad 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -9,6 +9,12 @@ compatible = "qcom,msm8960"; interrupt-parent = <&intc>; + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + qcom,no-pc-write; + }; + intc: interrupt-controller@2000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 9e5dadb101eb..1eff4130cde0 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -9,6 +9,11 @@ compatible = "qcom,msm8974"; interrupt-parent = <&intc>; + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 7 0xf04>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index be5d2b09a363..4d4dfbb59f4b 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -64,6 +64,19 @@ clock-names = "timer", "pclk"; }; + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x10000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + pinctrl@20008000 { compatible = "rockchip,rk3066a-pinctrl"; reg = <0x20008000 0x150>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 1a26b03b3649..bb36596ea205 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -60,6 +60,19 @@ interrupts = <GIC_PPI 13 0xf04>; }; + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x8000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + pinctrl@20008000 { compatible = "rockchip,rk3188-pinctrl"; reg = <0x20008000 0xa0>, diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 0fcbcfd67de2..26e5a968d49d 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -26,6 +26,16 @@ compatible = "simple-bus"; ranges; + scu@1013c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1013c000 0x100>; + }; + + pmu@20004000 { + compatible = "rockchip,rk3066-pmu"; + reg = <0x20004000 0x100>; + }; + gic: interrupt-controller@1013d000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig index 2519d6de0640..01004640ee4d 100644 --- a/arch/arm/configs/bcm_defconfig +++ b/arch/arm/configs/bcm_defconfig @@ -79,6 +79,13 @@ CONFIG_HW_RANDOM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y # CONFIG_HWMON is not set +CONFIG_MFD_BCM590XX=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_USERSPACE_CONSUMER=y +CONFIG_REGULATOR_BCM590XX=y + CONFIG_VIDEO_OUTPUT_CONTROL=y CONFIG_FB=y CONFIG_BACKLIGHT_LCD_SUPPORT=y diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig deleted file mode 100644 index 1571bea48bed..000000000000 --- a/arch/arm/configs/da8xx_omapl_defconfig +++ /dev/null @@ -1,139 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CGROUPS=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_DAVINCI=y -CONFIG_ARCH_DAVINCI_DA830=y -CONFIG_ARCH_DAVINCI_DA850=y -CONFIG_MACH_DA8XX_DT=y -CONFIG_MACH_MITYOMAPL138=y -CONFIG_MACH_OMAPL138_HAWKBOARD=y -CONFIG_DAVINCI_RESET_CLOCKS=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_LEDS=y -CONFIG_USE_OF=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=m -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_ONDEMAND=m -CONFIG_CPU_IDLE=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_LRO is not set -CONFIG_NETFILTER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_FW_LOADER is not set -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=1 -CONFIG_BLK_DEV_RAM_SIZE=32768 -CONFIG_EEPROM_AT24=y -CONFIG_SCSI=m -CONFIG_BLK_DEV_SD=m -CONFIG_NETDEVICES=y -CONFIG_TUN=m -CONFIG_LXT_PHY=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_TI_DAVINCI_EMAC=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_NETCONSOLE=y -CONFIG_NETPOLL_TRAP=y -CONFIG_INPUT_MOUSEDEV=m -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=m -CONFIG_KEYBOARD_ATKBD=m -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_XTKBD=m -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_VT_CONSOLE is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_DAVINCI=y -CONFIG_PINCTRL_SINGLE=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DUMMY=y -CONFIG_REGULATOR_TPS6507X=y -CONFIG_FB=y -CONFIG_FB_DA8XX=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_SOC=m -CONFIG_SND_DAVINCI_SOC=m -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_DMADEVICES=y -CONFIG_TI_EDMA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_XFS_FS=m -CONFIG_INOTIFY=y -CONFIG_AUTOFS4_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_CRAMFS=y -CONFIG_MINIX_FS=m -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V3=y -CONFIG_SMB_FS=m -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_TIMER_STATS=y -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC_T10DIF=m diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index 932b932c8856..2a282c051cfd 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -20,9 +20,14 @@ CONFIG_ARCH_DAVINCI_DM644x=y CONFIG_ARCH_DAVINCI_DM355=y CONFIG_ARCH_DAVINCI_DM646x=y CONFIG_ARCH_DAVINCI_DM365=y +CONFIG_ARCH_DAVINCI_DA830=y +CONFIG_ARCH_DAVINCI_DA850=y +CONFIG_MACH_DA8XX_DT=y CONFIG_MACH_SFFSDR=y CONFIG_MACH_NEUROS_OSD2=y CONFIG_MACH_DM355_LEOPARD=y +CONFIG_MACH_MITYOMAPL138=y +CONFIG_MACH_OMAPL138_HAWKBOARD=y CONFIG_DAVINCI_MUX_DEBUG=y CONFIG_DAVINCI_MUX_WARNINGS=y CONFIG_DAVINCI_RESET_CLOCKS=y @@ -32,8 +37,18 @@ CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_LEDS=y +CONFIG_USE_OF=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=m +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_IDLE=y CONFIG_PM_RUNTIME=y CONFIG_NET=y CONFIG_PACKET=y @@ -57,6 +72,7 @@ CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_PHYSMAP=m CONFIG_MTD_NAND=m CONFIG_MTD_NAND_DAVINCI=m +CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 @@ -71,6 +87,7 @@ CONFIG_TUN=m CONFIG_LXT_PHY=y CONFIG_LSI_ET1011C_PHY=y CONFIG_NET_ETHERNET=y +CONFIG_MII=y CONFIG_TI_DAVINCI_EMAC=y CONFIG_DM9000=y # CONFIG_NETDEV_1000 is not set @@ -97,15 +114,21 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=3 # CONFIG_HW_RANDOM is not set +CONFIG_SERIAL_OF_PLATFORM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_DAVINCI=y +CONFIG_PINCTRL_SINGLE=y CONFIG_GPIO_PCF857X=y CONFIG_WATCHDOG=y CONFIG_DAVINCI_WATCHDOG=m CONFIG_MFD_DM355EVM_MSP=y +CONFIG_TPS6507X=y CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_TPS6507X=y CONFIG_FB=y +CONFIG_FB_DA8XX=y CONFIG_FIRMWARE_EDID=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index 6309ee52ccfc..f1aeb7d72712 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -154,6 +154,7 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_ESDHC_IMX=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 53e82c2523eb..09e974392fa1 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -39,6 +39,8 @@ CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y CONFIG_SOC_VF610=y +CONFIG_PCI=y +CONFIG_PCI_IMX6=y CONFIG_SMP=y CONFIG_VMSPLIT_2G=y CONFIG_PREEMPT_VOLUNTARY=y @@ -165,6 +167,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_REGULATOR_PFUZE100=y @@ -186,6 +189,7 @@ CONFIG_LCD_L4F00242T03=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y CONFIG_SOUND=y @@ -211,6 +215,7 @@ CONFIG_USB_GADGET=y CONFIG_USB_ETH=m CONFIG_USB_MASS_STORAGE=m CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_ESDHC_IMX=y @@ -225,6 +230,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y CONFIG_RTC_DRV_SNVS=y @@ -277,6 +283,7 @@ CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=m CONFIG_NLS_UTF8=y +CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y # CONFIG_SCHED_DEBUG is not set CONFIG_PROVE_LOCKING=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index ee6982976d66..4863cdc3fb95 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_XP=y CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM_5301X=y CONFIG_ARCH_BCM_MOBILE=y CONFIG_ARCH_BERLIN=y CONFIG_MACH_BERLIN_BG2=y @@ -55,6 +56,7 @@ CONFIG_ARCH_VEXPRESS_CA9X4=y CONFIG_ARCH_VIRT=y CONFIG_ARCH_WM8850=y CONFIG_ARCH_ZYNQ=y +CONFIG_NEON=y CONFIG_TRUSTED_FOUNDATIONS=y CONFIG_PCI=y CONFIG_PCI_MSI=y diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig index 0f4511d2849f..2ffba3d7b5a5 100644 --- a/arch/arm/configs/mvebu_defconfig +++ b/arch/arm/configs/mvebu_defconfig @@ -11,6 +11,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_XP=y +CONFIG_NEON=y # CONFIG_CACHE_L2X0 is not set # CONFIG_SWP_EMULATE is not set CONFIG_PCI=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 3a0b53d225e7..364ba38e40f3 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -28,6 +28,7 @@ CONFIG_ARCH_OMAP3=y CONFIG_ARCH_OMAP4=y CONFIG_SOC_OMAP5=y CONFIG_SOC_AM33XX=y +CONFIG_SOC_AM43XX=y CONFIG_SOC_DRA7XX=y CONFIG_ARM_THUMBEE=y CONFIG_ARM_ERRATA_411920=y diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig index bb00ccf00d66..ad396af68e47 100644 --- a/arch/arm/firmware/Kconfig +++ b/arch/arm/firmware/Kconfig @@ -11,6 +11,7 @@ menu "Firmware options" config TRUSTED_FOUNDATIONS bool "Trusted Foundations secure monitor support" depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS + default y help Some devices (including most Tegra-based consumer devices on the market) are booted with the Trusted Foundations secure monitor @@ -20,7 +21,7 @@ config TRUSTED_FOUNDATIONS This option allows the kernel to invoke the secure monitor whenever required on devices using Trusted Foundations. See arch/arm/include/asm/trusted_foundations.h or the - tl,trusted-foundations device tree binding documentation for details + tlm,trusted-foundations device tree binding documentation for details on how to use it. Say n if you don't know what this is about. diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index ef1e3d8f4af0..3fb1b5a1dce9 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -22,6 +22,15 @@ #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 +#define TF_CPU_PM 0xfffffffc +#define TF_CPU_PM_S3 0xffffffe3 +#define TF_CPU_PM_S2 0xffffffe6 +#define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5 +#define TF_CPU_PM_S1 0xffffffe4 +#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7 + +static unsigned long cpu_boot_addr; + static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) { asm volatile( @@ -41,13 +50,22 @@ static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) { - tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0); + cpu_boot_addr = boot_addr; + tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0); + + return 0; +} + +static int tf_prepare_idle(void) +{ + tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr); return 0; } static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, + .prepare_idle = tf_prepare_idle, }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd) diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h index 15631300c238..2c9f10df7568 100644 --- a/arch/arm/include/asm/firmware.h +++ b/arch/arm/include/asm/firmware.h @@ -22,6 +22,10 @@ */ struct firmware_ops { /* + * Inform the firmware we intend to enter CPU idle mode + */ + int (*prepare_idle)(void); + /* * Enters CPU idle mode */ int (*do_idle)(void); diff --git a/arch/arm/plat-orion/include/plat/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h index 06f982d55697..12e1588dc4f1 100644 --- a/arch/arm/plat-orion/include/plat/cache-feroceon-l2.h +++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h @@ -1,5 +1,5 @@ /* - * arch/arm/plat-orion/include/plat/cache-feroceon-l2.h + * arch/arm/include/asm/hardware/cache-feroceon-l2.h * * Copyright (C) 2008 Marvell Semiconductor * @@ -9,3 +9,5 @@ */ extern void __init feroceon_l2_init(int l2_wt_override); +extern int __init feroceon_of_init(void); + diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 4157aec4e307..2ec765c39ab4 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -115,6 +115,15 @@ struct smp_operations { #endif }; +struct of_cpu_method { + const char *method; + struct smp_operations *ops; +}; + +#define CPU_METHOD_OF_DECLARE(name, _method, _ops) \ + static const struct of_cpu_method __cpu_method_of_table_##name \ + __used __section(__cpu_method_of_table) \ + = { .method = _method, .ops = _ops } /* * set platform specific SMP operations */ diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h index 3bd36e2c5f2e..b5f7705abcb0 100644 --- a/arch/arm/include/asm/trusted_foundations.h +++ b/arch/arm/include/asm/trusted_foundations.h @@ -30,6 +30,8 @@ #include <linux/printk.h> #include <linux/bug.h> #include <linux/of.h> +#include <linux/cpu.h> +#include <linux/smp.h> struct trusted_foundations_platform_data { unsigned int version_major; @@ -47,10 +49,13 @@ static inline void register_trusted_foundations( struct trusted_foundations_platform_data *pd) { /* - * If we try to register TF, this means the system needs it to continue. - * Its absence if thus a fatal error. + * If the system requires TF and we cannot provide it, continue booting + * but disable features that cannot be provided. */ - panic("No support for Trusted Foundations, stopping...\n"); + pr_err("No support for Trusted Foundations, continuing in degraded mode.\n"); + pr_err("Secondary processors as well as CPU PM will be disabled.\n"); + setup_max_cpus = 0; + cpu_idle_poll_ctrl(true); } static inline void of_register_trusted_foundations(void) @@ -59,7 +64,7 @@ static inline void of_register_trusted_foundations(void) * If we find the target should enable TF but does not support it, * fail as the system won't be able to do much anyway */ - if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations")) + if (of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations")) register_trusted_foundations(NULL); } #endif /* CONFIG_TRUSTED_FOUNDATIONS */ diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index f751714d52c1..c7419a585ddc 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -18,6 +18,7 @@ #include <linux/of_fdt.h> #include <linux/of_irq.h> #include <linux/of_platform.h> +#include <linux/smp.h> #include <asm/cputype.h> #include <asm/setup.h> @@ -63,6 +64,34 @@ void __init arm_dt_memblock_reserve(void) } } +#ifdef CONFIG_SMP +extern struct of_cpu_method __cpu_method_of_table_begin[]; +extern struct of_cpu_method __cpu_method_of_table_end[]; + +static int __init set_smp_ops_by_method(struct device_node *node) +{ + const char *method; + struct of_cpu_method *m = __cpu_method_of_table_begin; + + if (of_property_read_string(node, "enable-method", &method)) + return 0; + + for (; m < __cpu_method_of_table_end; m++) + if (!strcmp(m->method, method)) { + smp_set_ops(m->ops); + return 1; + } + + return 0; +} +#else +static inline int set_smp_ops_by_method(struct device_node *node) +{ + return 1; +} +#endif + + /* * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree * and builds the cpu logical map array containing MPIDR values related to @@ -79,6 +108,7 @@ void __init arm_dt_init_cpu_maps(void) * read as 0. */ struct device_node *cpu, *cpus; + int found_method = 0; u32 i, j, cpuidx = 1; u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; @@ -150,8 +180,18 @@ void __init arm_dt_init_cpu_maps(void) } tmp_map[i] = hwid; + + if (!found_method) + found_method = set_smp_ops_by_method(cpu); } + /* + * Fallback to an enable-method in the cpus node if nothing found in + * a cpu node. + */ + if (!found_method) + set_smp_ops_by_method(cpus); + if (!bootcpu_valid) { pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n"); return; diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 396d05c8b570..49c914cd9c7a 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -43,6 +43,32 @@ config ARCH_BCM2835 This enables support for the Broadcom BCM2835 SoC. This SoC is used in the Raspberry Pi and Roku 2 devices. +config ARCH_BCM_5301X + bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 + depends on MMU + select ARM_GIC + select CACHE_L2X0 + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select HAVE_SMP + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select ARM_GLOBAL_TIMER + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK + select MIGHT_HAVE_PCI + help + Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. + + This is a network SoC line mostly used in home routers and + wifi access points, it's internal name is Northstar. + This inclused the following SoC: BCM53010, BCM53011, BCM53012, + BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707, + BCM4708 and BCM4709. + + Do not confuse this with the BCM4760 which is a totally + different SoC or with the older BCM47XX and BCM53XX based + network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx + endmenu endif diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 0ad293882079..a326b28c4406 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2012-2013 Broadcom Corporation +# Copyright (C) 2012-2014 Broadcom Corporation # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -10,8 +10,10 @@ # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o +obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o board_bcm21664.o \ + bcm_kona_smc.o bcm_kona_smc_asm.o kona.o obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) +obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c new file mode 100644 index 000000000000..edff69761e04 --- /dev/null +++ b/arch/arm/mach-bcm/bcm_5301x.c @@ -0,0 +1,61 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * + * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ +#include <linux/of_platform.h> +#include <asm/hardware/cache-l2x0.h> + +#include <asm/mach/arch.h> +#include <asm/siginfo.h> +#include <asm/signal.h> + + +static bool first_fault = true; + +static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + if (fsr == 0x1c06 && first_fault) { + first_fault = false; + + /* + * These faults with code 0x1c06 happens for no good reason, + * possibly left over from the CFE boot loader. + */ + pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n", + addr, fsr); + + /* Returning non-zero causes fault display and panic */ + return 0; + } + + /* Others should cause a fault */ + return 1; +} + +static void __init bcm5301x_init_early(void) +{ + /* Install our hook */ + hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR, + "imprecise external abort"); +} + +static void __init bcm5301x_dt_init(void) +{ + l2x0_of_init(0, ~0UL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char __initconst *bcm5301x_dt_compat[] = { + "brcm,bcm4708", + NULL, +}; + +DT_MACHINE_START(BCM5301X, "BCM5301X") + .init_early = bcm5301x_init_early, + .init_machine = bcm5301x_dt_init, + .dt_compat = bcm5301x_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c new file mode 100644 index 000000000000..acc1573fd005 --- /dev/null +++ b/arch/arm/mach-bcm/board_bcm21664.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clocksource.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> + +#include <asm/mach/arch.h> + +#include "bcm_kona_smc.h" +#include "kona.h" + +#define RSTMGR_DT_STRING "brcm,bcm21664-resetmgr" + +#define RSTMGR_REG_WR_ACCESS_OFFSET 0 +#define RSTMGR_REG_CHIP_SOFT_RST_OFFSET 4 + +#define RSTMGR_WR_PASSWORD 0xa5a5 +#define RSTMGR_WR_PASSWORD_SHIFT 8 +#define RSTMGR_WR_ACCESS_ENABLE 1 + +static void bcm21664_restart(enum reboot_mode mode, const char *cmd) +{ + void __iomem *base; + struct device_node *resetmgr; + + resetmgr = of_find_compatible_node(NULL, NULL, RSTMGR_DT_STRING); + if (!resetmgr) { + pr_emerg("Couldn't find " RSTMGR_DT_STRING "\n"); + return; + } + base = of_iomap(resetmgr, 0); + if (!base) { + pr_emerg("Couldn't map " RSTMGR_DT_STRING "\n"); + return; + } + + /* + * A soft reset is triggered by writing a 0 to bit 0 of the soft reset + * register. To write to that register we must first write the password + * and the enable bit in the write access enable register. + */ + writel((RSTMGR_WR_PASSWORD << RSTMGR_WR_PASSWORD_SHIFT) | + RSTMGR_WR_ACCESS_ENABLE, + base + RSTMGR_REG_WR_ACCESS_OFFSET); + writel(0, base + RSTMGR_REG_CHIP_SOFT_RST_OFFSET); + + /* Wait for reset */ + while (1); +} + +static void __init bcm21664_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, + &platform_bus); + kona_l2_cache_init(); +} + +static const char * const bcm21664_dt_compat[] = { + "brcm,bcm21664", + NULL, +}; + +DT_MACHINE_START(BCM21664_DT, "BCM21664 Broadcom Application Processor") + .init_machine = bcm21664_init, + .restart = bcm21664_restart, + .dt_compat = bcm21664_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c index 5f831133178f..d62ca16d5394 100644 --- a/arch/arm/mach-clps711x/board-autcpu12.c +++ b/arch/arm/mach-clps711x/board-autcpu12.c @@ -265,14 +265,12 @@ static void __init autcpu12_init_late(void) MACHINE_START(AUTCPU12, "autronix autcpu12") /* Maintainer: Thomas Gleixner */ .atag_offset = 0x20000, - .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = autcpu12_init, .init_late = autcpu12_init_late, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c index a9e38c6bcfb4..e261a47f2aff 100644 --- a/arch/arm/mach-clps711x/board-cdb89712.c +++ b/arch/arm/mach-clps711x/board-cdb89712.c @@ -139,12 +139,10 @@ static void __init cdb89712_init(void) MACHINE_START(CDB89712, "Cirrus-CDB89712") /* Maintainer: Ray Lehtiniemi */ .atag_offset = 0x100, - .nr_irqs = CLPS711X_NR_IRQS, .map_io = clps711x_map_io, .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, .init_machine = cdb89712_init, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c index b4764246d0f8..221b9de32dd6 100644 --- a/arch/arm/mach-clps711x/board-clep7312.c +++ b/arch/arm/mach-clps711x/board-clep7312.c @@ -36,12 +36,10 @@ fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi) MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312") /* Maintainer: Nobody */ .atag_offset = 0x0100, - .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_clep7312, .map_io = clps711x_map_io, .init_early = clps711x_init_early, .init_irq = clps711x_init_irq, .init_time = clps711x_timer_init, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c index fe6184ead896..077609841f14 100644 --- a/arch/arm/mach-clps711x/board-edb7211.c +++ b/arch/arm/mach-clps711x/board-edb7211.c @@ -177,7 +177,6 @@ static void __init edb7211_init_late(void) MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") /* Maintainer: Jon McClintock */ .atag_offset = VIDEORAM_SIZE + 0x100, - .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_edb7211, .reserve = edb7211_reserve, .map_io = clps711x_map_io, @@ -186,6 +185,5 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") .init_time = clps711x_timer_init, .init_machine = edb7211_init, .init_late = edb7211_init_late, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c index dd81b06f68fe..67b733744ed7 100644 --- a/arch/arm/mach-clps711x/board-p720t.c +++ b/arch/arm/mach-clps711x/board-p720t.c @@ -363,7 +363,6 @@ static void __init p720t_init_late(void) MACHINE_START(P720T, "ARM-Prospector720T") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .atag_offset = 0x100, - .nr_irqs = CLPS711X_NR_IRQS, .fixup = fixup_p720t, .map_io = clps711x_map_io, .init_early = clps711x_init_early, @@ -371,6 +370,5 @@ MACHINE_START(P720T, "ARM-Prospector720T") .init_time = clps711x_timer_init, .init_machine = p720t_init, .init_late = p720t_init_late, - .handle_irq = clps711x_handle_irq, .restart = clps711x_restart, MACHINE_END diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index a1935911e4f1..aee81fa46ccf 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c @@ -31,14 +31,14 @@ #include <linux/clk-provider.h> #include <linux/sched_clock.h> -#include <asm/exception.h> -#include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <asm/system_misc.h> #include <mach/hardware.h> +#include "common.h" + static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh, *clk_tint, *clk_spi; @@ -59,204 +59,9 @@ void __init clps711x_map_io(void) iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc)); } -static void int1_mask(struct irq_data *d) -{ - u32 intmr1; - - intmr1 = clps_readl(INTMR1); - intmr1 &= ~(1 << d->irq); - clps_writel(intmr1, INTMR1); -} - -static void int1_eoi(struct irq_data *d) -{ - switch (d->irq) { - case IRQ_CSINT: clps_writel(0, COEOI); break; - case IRQ_TC1OI: clps_writel(0, TC1EOI); break; - case IRQ_TC2OI: clps_writel(0, TC2EOI); break; - case IRQ_RTCMI: clps_writel(0, RTCEOI); break; - case IRQ_TINT: clps_writel(0, TEOI); break; - case IRQ_UMSINT: clps_writel(0, UMSEOI); break; - } -} - -static void int1_unmask(struct irq_data *d) -{ - u32 intmr1; - - intmr1 = clps_readl(INTMR1); - intmr1 |= 1 << d->irq; - clps_writel(intmr1, INTMR1); -} - -static struct irq_chip int1_chip = { - .name = "Interrupt Vector 1", - .irq_eoi = int1_eoi, - .irq_mask = int1_mask, - .irq_unmask = int1_unmask, -}; - -static void int2_mask(struct irq_data *d) -{ - u32 intmr2; - - intmr2 = clps_readl(INTMR2); - intmr2 &= ~(1 << (d->irq - 16)); - clps_writel(intmr2, INTMR2); -} - -static void int2_eoi(struct irq_data *d) -{ - switch (d->irq) { - case IRQ_KBDINT: clps_writel(0, KBDEOI); break; - } -} - -static void int2_unmask(struct irq_data *d) -{ - u32 intmr2; - - intmr2 = clps_readl(INTMR2); - intmr2 |= 1 << (d->irq - 16); - clps_writel(intmr2, INTMR2); -} - -static struct irq_chip int2_chip = { - .name = "Interrupt Vector 2", - .irq_eoi = int2_eoi, - .irq_mask = int2_mask, - .irq_unmask = int2_unmask, -}; - -static void int3_mask(struct irq_data *d) -{ - u32 intmr3; - - intmr3 = clps_readl(INTMR3); - intmr3 &= ~(1 << (d->irq - 32)); - clps_writel(intmr3, INTMR3); -} - -static void int3_unmask(struct irq_data *d) -{ - u32 intmr3; - - intmr3 = clps_readl(INTMR3); - intmr3 |= 1 << (d->irq - 32); - clps_writel(intmr3, INTMR3); -} - -static struct irq_chip int3_chip = { - .name = "Interrupt Vector 3", - .irq_mask = int3_mask, - .irq_unmask = int3_unmask, -}; - -static struct { - int nr; - struct irq_chip *chip; - irq_flow_handler_t handle; -} clps711x_irqdescs[] __initdata = { - { IRQ_CSINT, &int1_chip, handle_fasteoi_irq, }, - { IRQ_EINT1, &int1_chip, handle_level_irq, }, - { IRQ_EINT2, &int1_chip, handle_level_irq, }, - { IRQ_EINT3, &int1_chip, handle_level_irq, }, - { IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, }, - { IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, }, - { IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, }, - { IRQ_TINT, &int1_chip, handle_fasteoi_irq, }, - { IRQ_UTXINT1, &int1_chip, handle_level_irq, }, - { IRQ_URXINT1, &int1_chip, handle_level_irq, }, - { IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, }, - { IRQ_SSEOTI, &int1_chip, handle_level_irq, }, - { IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, }, - { IRQ_SS2RX, &int2_chip, handle_level_irq, }, - { IRQ_SS2TX, &int2_chip, handle_level_irq, }, - { IRQ_UTXINT2, &int2_chip, handle_level_irq, }, - { IRQ_URXINT2, &int2_chip, handle_level_irq, }, -}; - void __init clps711x_init_irq(void) { - unsigned int i; - - /* Disable interrupts */ - clps_writel(0, INTMR1); - clps_writel(0, INTMR2); - clps_writel(0, INTMR3); - - /* Clear down any pending interrupts */ - clps_writel(0, BLEOI); - clps_writel(0, MCEOI); - clps_writel(0, COEOI); - clps_writel(0, TC1EOI); - clps_writel(0, TC2EOI); - clps_writel(0, RTCEOI); - clps_writel(0, TEOI); - clps_writel(0, UMSEOI); - clps_writel(0, KBDEOI); - clps_writel(0, SRXEOF); - clps_writel(0xffffffff, DAISR); - - for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) { - irq_set_chip_and_handler(clps711x_irqdescs[i].nr, - clps711x_irqdescs[i].chip, - clps711x_irqdescs[i].handle); - set_irq_flags(clps711x_irqdescs[i].nr, - IRQF_VALID | IRQF_PROBE); - } - - if (IS_ENABLED(CONFIG_FIQ)) { - init_FIQ(0); - irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip, - handle_bad_irq); - set_irq_flags(IRQ_DAIINT, - IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); - } -} - -static inline u32 fls16(u32 x) -{ - u32 r = 15; - - if (!(x & 0xff00)) { - x <<= 8; - r -= 8; - } - if (!(x & 0xf000)) { - x <<= 4; - r -= 4; - } - if (!(x & 0xc000)) { - x <<= 2; - r -= 2; - } - if (!(x & 0x8000)) - r--; - - return r; -} - -asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) -{ - do { - u32 irqstat; - void __iomem *base = CLPS711X_VIRT_BASE; - - irqstat = readw_relaxed(base + INTSR1) & - readw_relaxed(base + INTMR1); - if (irqstat) - handle_IRQ(fls16(irqstat), regs); - - irqstat = readw_relaxed(base + INTSR2) & - readw_relaxed(base + INTMR2); - if (irqstat) { - handle_IRQ(fls16(irqstat) + 16, regs); - continue; - } - - break; - } while (1); + clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K); } static u64 notrace clps711x_sched_clock_read(void) diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h index 9a6767bfdc47..7489139d5d63 100644 --- a/arch/arm/mach-clps711x/common.h +++ b/arch/arm/mach-clps711x/common.h @@ -6,13 +6,14 @@ #include <linux/reboot.h> -#define CLPS711X_NR_IRQS (33) #define CLPS711X_NR_GPIO (4 * 8 + 3) #define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit)) extern void clps711x_map_io(void); extern void clps711x_init_irq(void); extern void clps711x_timer_init(void); -extern void clps711x_handle_irq(struct pt_regs *regs); extern void clps711x_restart(enum reboot_mode mode, const char *cmd); extern void clps711x_init_early(void); + +/* drivers/irqchip/irq-clps711x.c */ +void clps711x_intc_init(phys_addr_t, resource_size_t); diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h index 0286f4bf9945..eb052a11aa9d 100644 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ b/arch/arm/mach-clps711x/include/mach/clps711x.h @@ -40,8 +40,6 @@ #define MEMCFG1 (0x0180) #define MEMCFG2 (0x01c0) #define DRFPR (0x0200) -#define INTSR1 (0x0240) -#define INTMR1 (0x0280) #define LCDCON (0x02c0) #define TC1D (0x0300) #define TC2D (0x0340) @@ -55,28 +53,16 @@ #define PALLSW (0x0540) #define PALMSW (0x0580) #define STFCLR (0x05c0) -#define BLEOI (0x0600) -#define MCEOI (0x0640) -#define TEOI (0x0680) -#define TC1EOI (0x06c0) -#define TC2EOI (0x0700) -#define RTCEOI (0x0740) -#define UMSEOI (0x0780) -#define COEOI (0x07c0) #define HALT (0x0800) #define STDBY (0x0840) #define FBADDR (0x1000) #define SYSCON2 (0x1100) #define SYSFLG2 (0x1140) -#define INTSR2 (0x1240) -#define INTMR2 (0x1280) #define UARTDR2 (0x1480) #define UBRLCR2 (0x14c0) #define SS2DR (0x1500) -#define SRXEOF (0x1600) #define SS2POP (0x16c0) -#define KBDEOI (0x1700) #define DAIR (0x2000) #define DAIDR0 (0x2040) @@ -84,8 +70,6 @@ #define DAIDR2 (0x20c0) #define DAISR (0x2100) #define SYSCON3 (0x2200) -#define INTSR3 (0x2240) -#define INTMR3 (0x2280) #define LEDFLSH (0x22c0) #define SDCONF (0x2300) #define SDRFPR (0x2340) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 626d2b82d0f3..db18ef866593 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -51,11 +51,6 @@ config ARCH_DAVINCI_DM365 select AINTC select ARCH_DAVINCI_DMx -config ARCH_DAVINCI_TNETV107X - bool "TNETV107X based system" - select CPU_V6 - select CP_INTC - comment "DaVinci Board Type" config MACH_DA8XX_DT @@ -215,13 +210,6 @@ config DA850_WL12XX AM18x EVM. -config MACH_TNETV107X - bool "TI TNETV107X Reference Platform" - default ARCH_DAVINCI_TNETV107X - depends on ARCH_DAVINCI_TNETV107X - help - Say Y here to select the TI TNETV107X Evaluation Module. - config MACH_MITYOMAPL138 bool "Critical Link MityDSP-L138/MityARM-1808 SoM" depends on ARCH_DAVINCI_DA850 diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 63997a1128e6..2204239ed243 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o -obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += tnetv107x.o devices-tnetv107x.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o @@ -32,7 +31,6 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o -obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot index 04a6c4e67b14..4b81601754a2 100644 --- a/arch/arm/mach-davinci/Makefile.boot +++ b/arch/arm/mach-davinci/Makefile.boot @@ -1,13 +1,7 @@ -ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y) -ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y) -$(error Cannot enable DaVinci and DA8XX platforms concurrently) -else - zreladdr-y += 0xc0008000 -params_phys-y := 0xc0000100 -initrd_phys-y := 0xc0800000 -endif -else - zreladdr-y += 0x80008000 -params_phys-y := 0x80000100 -initrd_phys-y := 0x80800000 -endif +zreladdr-$(CONFIG_ARCH_DAVINCI_DA8XX) += 0xc0008000 +params_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0000100 +initrd_phys-$(CONFIG_ARCH_DAVINCI_DA8XX) := 0xc0800000 + +zreladdr-$(CONFIG_ARCH_DAVINCI_DMx) += 0x80008000 +params_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80000100 +initrd_phys-$(CONFIG_ARCH_DAVINCI_DMx) := 0x80800000 diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c deleted file mode 100644 index 78ea395d2aca..000000000000 --- a/arch/arm/mach-davinci/board-tnetv107x-evm.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Texas Instruments TNETV107X EVM Board Support - * - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/console.h> -#include <linux/dma-mapping.h> -#include <linux/interrupt.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/ratelimit.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/input.h> -#include <linux/input/matrix_keypad.h> -#include <linux/spi/spi.h> -#include <linux/platform_data/edma.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/irqs.h> -#include <mach/mux.h> -#include <mach/cp_intc.h> -#include <mach/tnetv107x.h> - -#define EVM_MMC_WP_GPIO 21 -#define EVM_MMC_CD_GPIO 24 -#define EVM_SPI_CS_GPIO 54 - -static int initialize_gpio(int gpio, char *desc) -{ - int ret; - - ret = gpio_request(gpio, desc); - if (ret < 0) { - pr_err_ratelimited("cannot open %s gpio\n", desc); - return -ENOSYS; - } - gpio_direction_input(gpio); - return gpio; -} - -static int mmc_get_cd(int index) -{ - static int gpio; - - if (!gpio) - gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect"); - - if (gpio < 0) - return gpio; - - return gpio_get_value(gpio) ? 0 : 1; -} - -static int mmc_get_ro(int index) -{ - static int gpio; - - if (!gpio) - gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect"); - - if (gpio < 0) - return gpio; - - return gpio_get_value(gpio) ? 1 : 0; -} - -static struct davinci_mmc_config mmc_config = { - .get_cd = mmc_get_cd, - .get_ro = mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static const short sdio1_pins[] __initconst = { - TNETV107X_SDIO1_CLK_1, TNETV107X_SDIO1_CMD_1, - TNETV107X_SDIO1_DATA0_1, TNETV107X_SDIO1_DATA1_1, - TNETV107X_SDIO1_DATA2_1, TNETV107X_SDIO1_DATA3_1, - TNETV107X_GPIO21, TNETV107X_GPIO24, - -1 -}; - -static const short uart1_pins[] __initconst = { - TNETV107X_UART1_RD, TNETV107X_UART1_TD, - -1 -}; - -static const short ssp_pins[] __initconst = { - TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2, - TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2, - TNETV107X_SSP1_3, -1 -}; - -static struct mtd_partition nand_partitions[] = { - /* bootloader (U-Boot, etc) in first 12 sectors */ - { - .name = "bootloader", - .offset = 0, - .size = (12*SZ_128K), - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M, - .mask_flags = 0, - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } -}; - -static struct davinci_nand_pdata nand_config = { - .mask_cle = 0x4000, - .mask_ale = 0x2000, - .parts = nand_partitions, - .nr_parts = ARRAY_SIZE(nand_partitions), - .ecc_mode = NAND_ECC_HW, - .bbt_options = NAND_BBT_USE_FLASH, - .ecc_bits = 1, -}; - -static struct davinci_uart_config serial_config __initconst = { - .enabled_uarts = BIT(1), -}; - -static const uint32_t keymap[] = { - KEY(0, 0, KEY_NUMERIC_1), - KEY(0, 1, KEY_NUMERIC_2), - KEY(0, 2, KEY_NUMERIC_3), - KEY(0, 3, KEY_FN_F1), - KEY(0, 4, KEY_MENU), - - KEY(1, 0, KEY_NUMERIC_4), - KEY(1, 1, KEY_NUMERIC_5), - KEY(1, 2, KEY_NUMERIC_6), - KEY(1, 3, KEY_UP), - KEY(1, 4, KEY_FN_F2), - - KEY(2, 0, KEY_NUMERIC_7), - KEY(2, 1, KEY_NUMERIC_8), - KEY(2, 2, KEY_NUMERIC_9), - KEY(2, 3, KEY_LEFT), - KEY(2, 4, KEY_ENTER), - - KEY(3, 0, KEY_NUMERIC_STAR), - KEY(3, 1, KEY_NUMERIC_0), - KEY(3, 2, KEY_NUMERIC_POUND), - KEY(3, 3, KEY_DOWN), - KEY(3, 4, KEY_RIGHT), - - KEY(4, 0, KEY_FN_F3), - KEY(4, 1, KEY_FN_F4), - KEY(4, 2, KEY_MUTE), - KEY(4, 3, KEY_HOME), - KEY(4, 4, KEY_BACK), - - KEY(5, 0, KEY_VOLUMEDOWN), - KEY(5, 1, KEY_VOLUMEUP), - KEY(5, 2, KEY_F1), - KEY(5, 3, KEY_F2), - KEY(5, 4, KEY_F3), -}; - -static const struct matrix_keymap_data keymap_data = { - .keymap = keymap, - .keymap_size = ARRAY_SIZE(keymap), -}; - -static struct matrix_keypad_platform_data keypad_config = { - .keymap_data = &keymap_data, - .num_row_gpios = 6, - .num_col_gpios = 5, - .debounce_ms = 0, /* minimum */ - .active_low = 0, /* pull up realization */ - .no_autorepeat = 0, -}; - -static void spi_select_device(int cs) -{ - static int gpio; - - if (!gpio) { - int ret; - ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel"); - if (ret < 0) { - pr_err("cannot open spi chipsel gpio\n"); - gpio = -ENOSYS; - return; - } else { - gpio = EVM_SPI_CS_GPIO; - gpio_direction_output(gpio, 0); - } - } - - if (gpio < 0) - return; - - return gpio_set_value(gpio, cs ? 1 : 0); -} - -static struct ti_ssp_spi_data spi_master_data = { - .num_cs = 2, - .select = spi_select_device, - .iosel = SSP_PIN_SEL(0, SSP_CLOCK) | SSP_PIN_SEL(1, SSP_DATA) | - SSP_PIN_SEL(2, SSP_CHIPSEL) | SSP_PIN_SEL(3, SSP_IN) | - SSP_INPUT_SEL(3), -}; - -static struct ti_ssp_data ssp_config = { - .out_clock = 250 * 1000, - .dev_data = { - [1] = { - .dev_name = "ti-ssp-spi", - .pdata = &spi_master_data, - .pdata_size = sizeof(spi_master_data), - }, - }, -}; - -static struct tnetv107x_device_info evm_device_info __initconst = { - .serial_config = &serial_config, - .mmc_config[1] = &mmc_config, /* controller 1 */ - .nand_config[0] = &nand_config, /* chip select 0 */ - .keypad_config = &keypad_config, - .ssp_config = &ssp_config, -}; - -static struct spi_board_info spi_info[] __initconst = { -}; - -static __init void tnetv107x_evm_board_init(void) -{ - davinci_cfg_reg_list(sdio1_pins); - davinci_cfg_reg_list(uart1_pins); - davinci_cfg_reg_list(ssp_pins); - - tnetv107x_devices_init(&evm_device_info); - - spi_register_board_info(spi_info, ARRAY_SIZE(spi_info)); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init tnetv107x_evm_console_init(void) -{ - return add_preferred_console("ttyS", 0, "115200"); -} -console_initcall(tnetv107x_evm_console_init); -#endif - -MACHINE_START(TNETV107X, "TNETV107X EVM") - .atag_offset = 0x100, - .map_io = tnetv107x_init, - .init_irq = cp_intc_init, - .init_time = davinci_timer_init, - .init_machine = tnetv107x_evm_board_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, - .restart = tnetv107x_restart, -MACHINE_END diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 2eebc4338802..4ffc37accce0 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -79,6 +79,8 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata); #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 +int davinci_init_wdt(void); + /* DM355 function declarations */ void dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c deleted file mode 100644 index 01d8686e553c..000000000000 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ /dev/null @@ -1,434 +0,0 @@ -/* - * Texas Instruments TNETV107X SoC devices - * - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/clk.h> -#include <linux/slab.h> -#include <linux/platform_data/edma.h> - -#include <mach/common.h> -#include <mach/irqs.h> -#include <mach/tnetv107x.h> - -#include "clock.h" - -/* Base addresses for on-chip devices */ -#define TNETV107X_TPCC_BASE 0x01c00000 -#define TNETV107X_TPTC0_BASE 0x01c10000 -#define TNETV107X_TPTC1_BASE 0x01c10400 -#define TNETV107X_WDOG_BASE 0x08086700 -#define TNETV107X_TSC_BASE 0x08088500 -#define TNETV107X_SDIO0_BASE 0x08088700 -#define TNETV107X_SDIO1_BASE 0x08088800 -#define TNETV107X_KEYPAD_BASE 0x08088a00 -#define TNETV107X_SSP_BASE 0x08088c00 -#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 -#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 - -/* TNETV107X specific EDMA3 information */ -#define EDMA_TNETV107X_NUM_DMACH 64 -#define EDMA_TNETV107X_NUM_TCC 64 -#define EDMA_TNETV107X_NUM_PARAMENTRY 128 -#define EDMA_TNETV107X_NUM_EVQUE 2 -#define EDMA_TNETV107X_NUM_TC 2 -#define EDMA_TNETV107X_CHMAP_EXIST 0 -#define EDMA_TNETV107X_NUM_REGIONS 4 -#define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u -#define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu - -#define TNETV107X_DMACH_SDIO0_RX 26 -#define TNETV107X_DMACH_SDIO0_TX 27 -#define TNETV107X_DMACH_SDIO1_RX 28 -#define TNETV107X_DMACH_SDIO1_TX 29 - -static s8 edma_tc_mapping[][2] = { - /* event queue no TC no */ - { 0, 0 }, - { 1, 1 }, - { -1, -1 } -}; - -static s8 edma_priority_mapping[][2] = { - /* event queue no Prio */ - { 0, 3 }, - { 1, 7 }, - { -1, -1 } -}; - -static struct edma_soc_info edma_cc0_info = { - .n_channel = EDMA_TNETV107X_NUM_DMACH, - .n_region = EDMA_TNETV107X_NUM_REGIONS, - .n_slot = EDMA_TNETV107X_NUM_PARAMENTRY, - .n_tc = EDMA_TNETV107X_NUM_TC, - .n_cc = 1, - .queue_tc_mapping = edma_tc_mapping, - .queue_priority_mapping = edma_priority_mapping, - .default_queue = EVENTQ_1, -}; - -static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = { - &edma_cc0_info, -}; - -static struct resource edma_resources[] = { - { - .name = "edma_cc0", - .start = TNETV107X_TPCC_BASE, - .end = TNETV107X_TPCC_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc0", - .start = TNETV107X_TPTC0_BASE, - .end = TNETV107X_TPTC0_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc1", - .start = TNETV107X_TPTC1_BASE, - .end = TNETV107X_TPTC1_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma0", - .start = IRQ_TNETV107X_TPCC, - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma0_err", - .start = IRQ_TNETV107X_TPCC_ERR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device edma_device = { - .name = "edma", - .id = -1, - .num_resources = ARRAY_SIZE(edma_resources), - .resource = edma_resources, - .dev.platform_data = tnetv107x_edma_info, -}; - -static struct plat_serial8250_port serial0_platform_data[] = { - { - .mapbase = TNETV107X_UART0_BASE, - .irq = IRQ_TNETV107X_UART0, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_FIXED_TYPE | UPF_IOREMAP, - .type = PORT_AR7, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port serial1_platform_data[] = { - { - .mapbase = TNETV107X_UART1_BASE, - .irq = IRQ_TNETV107X_UART1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_FIXED_TYPE | UPF_IOREMAP, - .type = PORT_AR7, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0, - } -}; -static struct plat_serial8250_port serial2_platform_data[] = { - { - .mapbase = TNETV107X_UART2_BASE, - .irq = IRQ_TNETV107X_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_FIXED_TYPE | UPF_IOREMAP, - .type = PORT_AR7, - .iotype = UPIO_MEM32, - .regshift = 2, - }, - { - .flags = 0, - } -}; - - -struct platform_device tnetv107x_serial_device[] = { - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = serial0_platform_data, - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev.platform_data = serial1_platform_data, - }, - { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev.platform_data = serial2_platform_data, - }, - { - } -}; - -static struct resource mmc0_resources[] = { - { /* Memory mapped registers */ - .start = TNETV107X_SDIO0_BASE, - .end = TNETV107X_SDIO0_BASE + 0x0ff, - .flags = IORESOURCE_MEM - }, - { /* MMC interrupt */ - .start = IRQ_TNETV107X_MMC0, - .flags = IORESOURCE_IRQ - }, - { /* SDIO interrupt */ - .start = IRQ_TNETV107X_SDIO0, - .flags = IORESOURCE_IRQ - }, - { /* DMA RX */ - .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX), - .flags = IORESOURCE_DMA - }, - { /* DMA TX */ - .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX), - .flags = IORESOURCE_DMA - }, -}; - -static struct resource mmc1_resources[] = { - { /* Memory mapped registers */ - .start = TNETV107X_SDIO1_BASE, - .end = TNETV107X_SDIO1_BASE + 0x0ff, - .flags = IORESOURCE_MEM - }, - { /* MMC interrupt */ - .start = IRQ_TNETV107X_MMC1, - .flags = IORESOURCE_IRQ - }, - { /* SDIO interrupt */ - .start = IRQ_TNETV107X_SDIO1, - .flags = IORESOURCE_IRQ - }, - { /* DMA RX */ - .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX), - .flags = IORESOURCE_DMA - }, - { /* DMA TX */ - .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX), - .flags = IORESOURCE_DMA - }, -}; - -static u64 mmc0_dma_mask = DMA_BIT_MASK(32); -static u64 mmc1_dma_mask = DMA_BIT_MASK(32); - -static struct platform_device mmc_devices[2] = { - { - .name = "dm6441-mmc", - .id = 0, - .dev = { - .dma_mask = &mmc0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmc0_resources), - .resource = mmc0_resources - }, - { - .name = "dm6441-mmc", - .id = 1, - .dev = { - .dma_mask = &mmc1_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(mmc1_resources), - .resource = mmc1_resources - }, -}; - -static const u32 emif_windows[] = { - TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE, - TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE, -}; - -static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M }; - -static struct resource wdt_resources[] = { - { - .start = TNETV107X_WDOG_BASE, - .end = TNETV107X_WDOG_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device tnetv107x_wdt_device = { - .name = "tnetv107x_wdt", - .id = 0, - .num_resources = ARRAY_SIZE(wdt_resources), - .resource = wdt_resources, -}; - -static int __init nand_init(int chipsel, struct davinci_nand_pdata *data) -{ - struct resource res[2]; - struct platform_device *pdev; - u32 range; - int ret; - - /* Figure out the resource range from the ale/cle masks */ - range = max(data->mask_cle, data->mask_ale); - range = PAGE_ALIGN(range + 4) - 1; - - if (range >= emif_window_sizes[chipsel]) - return -EINVAL; - - pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); - if (!pdev) - return -ENOMEM; - - pdev->name = "davinci_nand"; - pdev->id = chipsel; - pdev->dev.platform_data = data; - - memset(res, 0, sizeof(res)); - - res[0].start = emif_windows[chipsel]; - res[0].end = res[0].start + range; - res[0].flags = IORESOURCE_MEM; - - res[1].start = TNETV107X_ASYNC_EMIF_CNTRL_BASE; - res[1].end = res[1].start + SZ_4K - 1; - res[1].flags = IORESOURCE_MEM; - - ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); - if (ret < 0) { - kfree(pdev); - return ret; - } - - return platform_device_register(pdev); -} - -static struct resource keypad_resources[] = { - { - .start = TNETV107X_KEYPAD_BASE, - .end = TNETV107X_KEYPAD_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_TNETV107X_KEYPAD, - .flags = IORESOURCE_IRQ, - .name = "press", - }, - { - .start = IRQ_TNETV107X_KEYPAD_FREE, - .flags = IORESOURCE_IRQ, - .name = "release", - }, -}; - -static struct platform_device keypad_device = { - .name = "tnetv107x-keypad", - .num_resources = ARRAY_SIZE(keypad_resources), - .resource = keypad_resources, -}; - -static struct resource tsc_resources[] = { - { - .start = TNETV107X_TSC_BASE, - .end = TNETV107X_TSC_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_TNETV107X_TSC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tsc_device = { - .name = "tnetv107x-ts", - .num_resources = ARRAY_SIZE(tsc_resources), - .resource = tsc_resources, -}; - -static struct resource ssp_resources[] = { - { - .start = TNETV107X_SSP_BASE, - .end = TNETV107X_SSP_BASE + 0x1ff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_TNETV107X_SSP, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ssp_device = { - .name = "ti-ssp", - .id = -1, - .num_resources = ARRAY_SIZE(ssp_resources), - .resource = ssp_resources, -}; - -void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) -{ - int i, error; - struct clk *tsc_clk; - - /* - * The reset defaults for tnetv107x tsc clock divider is set too high. - * This forces the clock down to a range that allows the ADC to - * complete sample conversion in time. - */ - tsc_clk = clk_get(NULL, "sys_tsc_clk"); - if (!IS_ERR(tsc_clk)) { - error = clk_set_rate(tsc_clk, 5000000); - WARN_ON(error < 0); - clk_put(tsc_clk); - } - - platform_device_register(&edma_device); - platform_device_register(&tnetv107x_wdt_device); - platform_device_register(&tsc_device); - - if (info->serial_config) - davinci_serial_init(tnetv107x_serial_device); - - for (i = 0; i < 2; i++) - if (info->mmc_config[i]) { - mmc_devices[i].dev.platform_data = info->mmc_config[i]; - platform_device_register(&mmc_devices[i]); - } - - for (i = 0; i < 4; i++) - if (info->nand_config[i]) - nand_init(i, info->nand_config[i]); - - if (info->keypad_config) { - keypad_device.dev.platform_data = info->keypad_config; - platform_device_register(&keypad_device); - } - - if (info->ssp_config) { - ssp_device.dev.platform_data = info->ssp_config; - platform_device_register(&ssp_device); - } -} diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 5cf9a027dcc6..6257aa452568 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -313,9 +313,9 @@ void davinci_restart(enum reboot_mode mode, const char *cmd) davinci_watchdog_reset(&davinci_wdt_device); } -static void davinci_init_wdt(void) +int davinci_init_wdt(void) { - platform_device_register(&davinci_wdt_device); + return platform_device_register(&davinci_wdt_device); } static struct platform_device davinci_gpio_device = { @@ -348,16 +348,3 @@ struct davinci_timer_instance davinci_timer_instance[2] = { }, }; -/*-------------------------------------------------------------------------*/ - -static int __init davinci_init_devices(void) -{ - /* please keep these calls, and their implementations above, - * in alphabetical order so they're easier to sort through. - */ - davinci_init_wdt(); - - return 0; -} -arch_initcall(davinci_init_devices); - diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 4668c0e19767..07381d8cea62 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -1076,12 +1076,18 @@ int __init dm355_init_video(struct vpfe_config *vpfe_cfg, static int __init dm355_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm355()) return 0; davinci_cfg_reg(DM355_INT_EDMA_CC); platform_device_register(&dm355_edma_device); - return 0; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm355_init_devices); diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index b44b49e2801a..08a61b938333 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -1436,6 +1436,8 @@ int __init dm365_init_video(struct vpfe_config *vpfe_cfg, static int __init dm365_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm365()) return 0; @@ -1445,6 +1447,10 @@ static int __init dm365_init_devices(void) platform_device_register(&dm365_mdio_device); platform_device_register(&dm365_emac_device); - return 0; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm365_init_devices); diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 5c3e0be95ef3..5debffba4b24 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -964,6 +964,8 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, static int __init dm644x_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm644x()) return 0; @@ -972,6 +974,10 @@ static int __init dm644x_init_devices(void) platform_device_register(&dm644x_mdio_device); platform_device_register(&dm644x_emac_device); - return 0; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm644x_init_devices); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 81768dd47096..332d00d24dc2 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -955,12 +955,18 @@ void __init dm646x_init(void) static int __init dm646x_init_devices(void) { + int ret = 0; + if (!cpu_is_davinci_dm646x()) return 0; platform_device_register(&dm646x_mdio_device); platform_device_register(&dm646x_emac_device); - return 0; + ret = davinci_init_wdt(); + if (ret) + pr_warn("%s: watchdog init failed: %d\n", __func__, ret); + + return ret; } postcore_initcall(dm646x_init_devices); diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index 957fb87e832e..1fc84e21664d 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -33,7 +33,6 @@ struct davinci_id { #define DAVINCI_CPU_ID_DM365 0x03650000 #define DAVINCI_CPU_ID_DA830 0x08300000 #define DAVINCI_CPU_ID_DA850 0x08500000 -#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000 #define IS_DAVINCI_CPU(type, id) \ static inline int is_davinci_ ##type(void) \ @@ -47,7 +46,6 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) -IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() @@ -85,10 +83,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X) #define cpu_is_davinci_da850() 0 #endif -#ifdef CONFIG_ARCH_DAVINCI_TNETV107X -#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x() -#else -#define cpu_is_davinci_tnetv107x() 0 -#endif - #endif diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index ec76c7775c2e..354af71798dc 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -401,103 +401,6 @@ #define DA850_N_CP_INTC_IRQ 101 - -/* TNETV107X specific interrupts */ -#define IRQ_TNETV107X_TDM1_TXDMA 0 -#define IRQ_TNETV107X_EXT_INT_0 1 -#define IRQ_TNETV107X_EXT_INT_1 2 -#define IRQ_TNETV107X_GPIO_INT12 3 -#define IRQ_TNETV107X_GPIO_INT13 4 -#define IRQ_TNETV107X_TIMER_0_TINT12 5 -#define IRQ_TNETV107X_TIMER_1_TINT12 6 -#define IRQ_TNETV107X_UART0 7 -#define IRQ_TNETV107X_TDM1_RXDMA 8 -#define IRQ_TNETV107X_MCDMA_INT0 9 -#define IRQ_TNETV107X_MCDMA_INT1 10 -#define IRQ_TNETV107X_TPCC 11 -#define IRQ_TNETV107X_TPCC_INT0 12 -#define IRQ_TNETV107X_TPCC_INT1 13 -#define IRQ_TNETV107X_TPCC_INT2 14 -#define IRQ_TNETV107X_TPCC_INT3 15 -#define IRQ_TNETV107X_TPTC0 16 -#define IRQ_TNETV107X_TPTC1 17 -#define IRQ_TNETV107X_TIMER_0_TINT34 18 -#define IRQ_TNETV107X_ETHSS 19 -#define IRQ_TNETV107X_TIMER_1_TINT34 20 -#define IRQ_TNETV107X_DSP2ARM_INT0 21 -#define IRQ_TNETV107X_DSP2ARM_INT1 22 -#define IRQ_TNETV107X_ARM_NPMUIRQ 23 -#define IRQ_TNETV107X_USB1 24 -#define IRQ_TNETV107X_VLYNQ 25 -#define IRQ_TNETV107X_UART0_DMATX 26 -#define IRQ_TNETV107X_UART0_DMARX 27 -#define IRQ_TNETV107X_TDM1_TXMCSP 28 -#define IRQ_TNETV107X_SSP 29 -#define IRQ_TNETV107X_MCDMA_INT2 30 -#define IRQ_TNETV107X_MCDMA_INT3 31 -#define IRQ_TNETV107X_TDM_CODECIF_EOT 32 -#define IRQ_TNETV107X_IMCOP_SQR_ARM 33 -#define IRQ_TNETV107X_USB0 34 -#define IRQ_TNETV107X_USB_CDMA 35 -#define IRQ_TNETV107X_LCD 36 -#define IRQ_TNETV107X_KEYPAD 37 -#define IRQ_TNETV107X_KEYPAD_FREE 38 -#define IRQ_TNETV107X_RNG 39 -#define IRQ_TNETV107X_PKA 40 -#define IRQ_TNETV107X_TDM0_TXDMA 41 -#define IRQ_TNETV107X_TDM0_RXDMA 42 -#define IRQ_TNETV107X_TDM0_TXMCSP 43 -#define IRQ_TNETV107X_TDM0_RXMCSP 44 -#define IRQ_TNETV107X_TDM1_RXMCSP 45 -#define IRQ_TNETV107X_SDIO1 46 -#define IRQ_TNETV107X_SDIO0 47 -#define IRQ_TNETV107X_TSC 48 -#define IRQ_TNETV107X_TS 49 -#define IRQ_TNETV107X_UART1 50 -#define IRQ_TNETV107X_MBX_LITE 51 -#define IRQ_TNETV107X_GPIO_INT00 52 -#define IRQ_TNETV107X_GPIO_INT01 53 -#define IRQ_TNETV107X_GPIO_INT02 54 -#define IRQ_TNETV107X_GPIO_INT03 55 -#define IRQ_TNETV107X_UART2 56 -#define IRQ_TNETV107X_UART2_DMATX 57 -#define IRQ_TNETV107X_UART2_DMARX 58 -#define IRQ_TNETV107X_IMCOP_IMX 59 -#define IRQ_TNETV107X_IMCOP_VLCD 60 -#define IRQ_TNETV107X_AES 61 -#define IRQ_TNETV107X_DES 62 -#define IRQ_TNETV107X_SHAMD5 63 -#define IRQ_TNETV107X_TPCC_ERR 68 -#define IRQ_TNETV107X_TPCC_PROT 69 -#define IRQ_TNETV107X_TPTC0_ERR 70 -#define IRQ_TNETV107X_TPTC1_ERR 71 -#define IRQ_TNETV107X_UART0_ERR 72 -#define IRQ_TNETV107X_UART1_ERR 73 -#define IRQ_TNETV107X_AEMIF_ERR 74 -#define IRQ_TNETV107X_DDR_ERR 75 -#define IRQ_TNETV107X_WDTARM_INT0 76 -#define IRQ_TNETV107X_MCDMA_ERR 77 -#define IRQ_TNETV107X_GPIO_ERR 78 -#define IRQ_TNETV107X_MPU_ADDR 79 -#define IRQ_TNETV107X_MPU_PROT 80 -#define IRQ_TNETV107X_IOPU_ADDR 81 -#define IRQ_TNETV107X_IOPU_PROT 82 -#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83 -#define IRQ_TNETV107X_WDT0_ADDR_ERR 84 -#define IRQ_TNETV107X_WDT1_ADDR_ERR 85 -#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86 -#define IRQ_TNETV107X_PLL_UNLOCK 87 -#define IRQ_TNETV107X_WDTDSP_INT0 88 -#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89 -#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90 -#define IRQ_TNETV107X_PBIST_CPU 91 -#define IRQ_TNETV107X_WDTARM 92 -#define IRQ_TNETV107X_PSC 93 -#define IRQ_TNETV107X_MMC0 94 -#define IRQ_TNETV107X_MMC1 95 - -#define TNETV107X_N_CP_INTC_IRQ 96 - /* da850 currently has the most gpio pins (144) */ #define DAVINCI_N_GPIO 144 /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 9e95b8a1edb6..631655e68ae0 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -972,275 +972,6 @@ enum davinci_da850_index { DA850_VPIF_CLKO3, }; -enum davinci_tnetv107x_index { - TNETV107X_ASR_A00, - TNETV107X_GPIO32, - TNETV107X_ASR_A01, - TNETV107X_GPIO33, - TNETV107X_ASR_A02, - TNETV107X_GPIO34, - TNETV107X_ASR_A03, - TNETV107X_GPIO35, - TNETV107X_ASR_A04, - TNETV107X_GPIO36, - TNETV107X_ASR_A05, - TNETV107X_GPIO37, - TNETV107X_ASR_A06, - TNETV107X_GPIO38, - TNETV107X_ASR_A07, - TNETV107X_GPIO39, - TNETV107X_ASR_A08, - TNETV107X_GPIO40, - TNETV107X_ASR_A09, - TNETV107X_GPIO41, - TNETV107X_ASR_A10, - TNETV107X_GPIO42, - TNETV107X_ASR_A11, - TNETV107X_BOOT_STRP_0, - TNETV107X_ASR_A12, - TNETV107X_BOOT_STRP_1, - TNETV107X_ASR_A13, - TNETV107X_GPIO43, - TNETV107X_ASR_A14, - TNETV107X_GPIO44, - TNETV107X_ASR_A15, - TNETV107X_GPIO45, - TNETV107X_ASR_A16, - TNETV107X_GPIO46, - TNETV107X_ASR_A17, - TNETV107X_GPIO47, - TNETV107X_ASR_A18, - TNETV107X_GPIO48, - TNETV107X_SDIO1_DATA3_0, - TNETV107X_ASR_A19, - TNETV107X_GPIO49, - TNETV107X_SDIO1_DATA2_0, - TNETV107X_ASR_A20, - TNETV107X_GPIO50, - TNETV107X_SDIO1_DATA1_0, - TNETV107X_ASR_A21, - TNETV107X_GPIO51, - TNETV107X_SDIO1_DATA0_0, - TNETV107X_ASR_A22, - TNETV107X_GPIO52, - TNETV107X_SDIO1_CMD_0, - TNETV107X_ASR_A23, - TNETV107X_GPIO53, - TNETV107X_SDIO1_CLK_0, - TNETV107X_ASR_BA_1, - TNETV107X_GPIO54, - TNETV107X_SYS_PLL_CLK, - TNETV107X_ASR_CS0, - TNETV107X_ASR_CS1, - TNETV107X_ASR_CS2, - TNETV107X_TDM_PLL_CLK, - TNETV107X_ASR_CS3, - TNETV107X_ETH_PHY_CLK, - TNETV107X_ASR_D00, - TNETV107X_GPIO55, - TNETV107X_ASR_D01, - TNETV107X_GPIO56, - TNETV107X_ASR_D02, - TNETV107X_GPIO57, - TNETV107X_ASR_D03, - TNETV107X_GPIO58, - TNETV107X_ASR_D04, - TNETV107X_GPIO59_0, - TNETV107X_ASR_D05, - TNETV107X_GPIO60_0, - TNETV107X_ASR_D06, - TNETV107X_GPIO61_0, - TNETV107X_ASR_D07, - TNETV107X_GPIO62_0, - TNETV107X_ASR_D08, - TNETV107X_GPIO63_0, - TNETV107X_ASR_D09, - TNETV107X_GPIO64_0, - TNETV107X_ASR_D10, - TNETV107X_SDIO1_DATA3_1, - TNETV107X_ASR_D11, - TNETV107X_SDIO1_DATA2_1, - TNETV107X_ASR_D12, - TNETV107X_SDIO1_DATA1_1, - TNETV107X_ASR_D13, - TNETV107X_SDIO1_DATA0_1, - TNETV107X_ASR_D14, - TNETV107X_SDIO1_CMD_1, - TNETV107X_ASR_D15, - TNETV107X_SDIO1_CLK_1, - TNETV107X_ASR_OE, - TNETV107X_BOOT_STRP_2, - TNETV107X_ASR_RNW, - TNETV107X_GPIO29_0, - TNETV107X_ASR_WAIT, - TNETV107X_GPIO30_0, - TNETV107X_ASR_WE, - TNETV107X_BOOT_STRP_3, - TNETV107X_ASR_WE_DQM0, - TNETV107X_GPIO31, - TNETV107X_LCD_PD17_0, - TNETV107X_ASR_WE_DQM1, - TNETV107X_ASR_BA0_0, - TNETV107X_VLYNQ_CLK, - TNETV107X_GPIO14, - TNETV107X_LCD_PD19_0, - TNETV107X_VLYNQ_RXD0, - TNETV107X_GPIO15, - TNETV107X_LCD_PD20_0, - TNETV107X_VLYNQ_RXD1, - TNETV107X_GPIO16, - TNETV107X_LCD_PD21_0, - TNETV107X_VLYNQ_TXD0, - TNETV107X_GPIO17, - TNETV107X_LCD_PD22_0, - TNETV107X_VLYNQ_TXD1, - TNETV107X_GPIO18, - TNETV107X_LCD_PD23_0, - TNETV107X_SDIO0_CLK, - TNETV107X_GPIO19, - TNETV107X_SDIO0_CMD, - TNETV107X_GPIO20, - TNETV107X_SDIO0_DATA0, - TNETV107X_GPIO21, - TNETV107X_SDIO0_DATA1, - TNETV107X_GPIO22, - TNETV107X_SDIO0_DATA2, - TNETV107X_GPIO23, - TNETV107X_SDIO0_DATA3, - TNETV107X_GPIO24, - TNETV107X_EMU0, - TNETV107X_EMU1, - TNETV107X_RTCK, - TNETV107X_TRST_N, - TNETV107X_TCK, - TNETV107X_TDI, - TNETV107X_TDO, - TNETV107X_TMS, - TNETV107X_TDM1_CLK, - TNETV107X_TDM1_RX, - TNETV107X_TDM1_TX, - TNETV107X_TDM1_FS, - TNETV107X_KEYPAD_R0, - TNETV107X_KEYPAD_R1, - TNETV107X_KEYPAD_R2, - TNETV107X_KEYPAD_R3, - TNETV107X_KEYPAD_R4, - TNETV107X_KEYPAD_R5, - TNETV107X_KEYPAD_R6, - TNETV107X_GPIO12, - TNETV107X_KEYPAD_R7, - TNETV107X_GPIO10, - TNETV107X_KEYPAD_C0, - TNETV107X_KEYPAD_C1, - TNETV107X_KEYPAD_C2, - TNETV107X_KEYPAD_C3, - TNETV107X_KEYPAD_C4, - TNETV107X_KEYPAD_C5, - TNETV107X_KEYPAD_C6, - TNETV107X_GPIO13, - TNETV107X_TEST_CLK_IN, - TNETV107X_KEYPAD_C7, - TNETV107X_GPIO11, - TNETV107X_SSP0_0, - TNETV107X_SCC_DCLK, - TNETV107X_LCD_PD20_1, - TNETV107X_SSP0_1, - TNETV107X_SCC_CS_N, - TNETV107X_LCD_PD21_1, - TNETV107X_SSP0_2, - TNETV107X_SCC_D, - TNETV107X_LCD_PD22_1, - TNETV107X_SSP0_3, - TNETV107X_SCC_RESETN, - TNETV107X_LCD_PD23_1, - TNETV107X_SSP1_0, - TNETV107X_GPIO25, - TNETV107X_UART2_CTS, - TNETV107X_SSP1_1, - TNETV107X_GPIO26, - TNETV107X_UART2_RD, - TNETV107X_SSP1_2, - TNETV107X_GPIO27, - TNETV107X_UART2_RTS, - TNETV107X_SSP1_3, - TNETV107X_GPIO28, - TNETV107X_UART2_TD, - TNETV107X_UART0_CTS, - TNETV107X_UART0_RD, - TNETV107X_UART0_RTS, - TNETV107X_UART0_TD, - TNETV107X_UART1_RD, - TNETV107X_UART1_TD, - TNETV107X_LCD_AC_NCS, - TNETV107X_LCD_HSYNC_RNW, - TNETV107X_LCD_VSYNC_A0, - TNETV107X_LCD_MCLK, - TNETV107X_LCD_PD16_0, - TNETV107X_LCD_PCLK_E, - TNETV107X_LCD_PD00, - TNETV107X_LCD_PD01, - TNETV107X_LCD_PD02, - TNETV107X_LCD_PD03, - TNETV107X_LCD_PD04, - TNETV107X_LCD_PD05, - TNETV107X_LCD_PD06, - TNETV107X_LCD_PD07, - TNETV107X_LCD_PD08, - TNETV107X_GPIO59_1, - TNETV107X_LCD_PD09, - TNETV107X_GPIO60_1, - TNETV107X_LCD_PD10, - TNETV107X_ASR_BA0_1, - TNETV107X_GPIO61_1, - TNETV107X_LCD_PD11, - TNETV107X_GPIO62_1, - TNETV107X_LCD_PD12, - TNETV107X_GPIO63_1, - TNETV107X_LCD_PD13, - TNETV107X_GPIO64_1, - TNETV107X_LCD_PD14, - TNETV107X_GPIO29_1, - TNETV107X_LCD_PD15, - TNETV107X_GPIO30_1, - TNETV107X_EINT0, - TNETV107X_GPIO08, - TNETV107X_EINT1, - TNETV107X_GPIO09, - TNETV107X_GPIO00, - TNETV107X_LCD_PD20_2, - TNETV107X_TDM_CLK_IN_2, - TNETV107X_GPIO01, - TNETV107X_LCD_PD21_2, - TNETV107X_24M_CLK_OUT_1, - TNETV107X_GPIO02, - TNETV107X_LCD_PD22_2, - TNETV107X_GPIO03, - TNETV107X_LCD_PD23_2, - TNETV107X_GPIO04, - TNETV107X_LCD_PD16_1, - TNETV107X_USB0_RXERR, - TNETV107X_GPIO05, - TNETV107X_LCD_PD17_1, - TNETV107X_TDM_CLK_IN_1, - TNETV107X_GPIO06, - TNETV107X_LCD_PD18, - TNETV107X_24M_CLK_OUT_2, - TNETV107X_GPIO07, - TNETV107X_LCD_PD19_1, - TNETV107X_USB1_RXERR, - TNETV107X_ETH_PLL_CLK, - TNETV107X_MDIO, - TNETV107X_MDC, - TNETV107X_AIC_MUTE_STAT_N, - TNETV107X_TDM0_CLK, - TNETV107X_AIC_HNS_EN_N, - TNETV107X_TDM0_FS, - TNETV107X_AIC_HDS_EN_STAT_N, - TNETV107X_TDM0_TX, - TNETV107X_AIC_HNF_EN_STAT_N, - TNETV107X_TDM0_RX, -}; - #define PINMUX(x) (4 * (x)) #ifdef CONFIG_DAVINCI_MUX diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 0a22710493fd..99d47cfa301f 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -182,53 +182,6 @@ #define DA8XX_LPSC1_CR_P3_SS 26 #define DA8XX_LPSC1_L3_CBA_RAM 31 -/* TNETV107X LPSC Assignments */ -#define TNETV107X_LPSC_ARM 0 -#define TNETV107X_LPSC_GEM 1 -#define TNETV107X_LPSC_DDR2_PHY 2 -#define TNETV107X_LPSC_TPCC 3 -#define TNETV107X_LPSC_TPTC0 4 -#define TNETV107X_LPSC_TPTC1 5 -#define TNETV107X_LPSC_RAM 6 -#define TNETV107X_LPSC_MBX_LITE 7 -#define TNETV107X_LPSC_LCD 8 -#define TNETV107X_LPSC_ETHSS 9 -#define TNETV107X_LPSC_AEMIF 10 -#define TNETV107X_LPSC_CHIP_CFG 11 -#define TNETV107X_LPSC_TSC 12 -#define TNETV107X_LPSC_ROM 13 -#define TNETV107X_LPSC_UART2 14 -#define TNETV107X_LPSC_PKTSEC 15 -#define TNETV107X_LPSC_SECCTL 16 -#define TNETV107X_LPSC_KEYMGR 17 -#define TNETV107X_LPSC_KEYPAD 18 -#define TNETV107X_LPSC_GPIO 19 -#define TNETV107X_LPSC_MDIO 20 -#define TNETV107X_LPSC_SDIO0 21 -#define TNETV107X_LPSC_UART0 22 -#define TNETV107X_LPSC_UART1 23 -#define TNETV107X_LPSC_TIMER0 24 -#define TNETV107X_LPSC_TIMER1 25 -#define TNETV107X_LPSC_WDT_ARM 26 -#define TNETV107X_LPSC_WDT_DSP 27 -#define TNETV107X_LPSC_SSP 28 -#define TNETV107X_LPSC_TDM0 29 -#define TNETV107X_LPSC_VLYNQ 30 -#define TNETV107X_LPSC_MCDMA 31 -#define TNETV107X_LPSC_USB0 32 -#define TNETV107X_LPSC_TDM1 33 -#define TNETV107X_LPSC_DEBUGSS 34 -#define TNETV107X_LPSC_ETHSS_RGMII 35 -#define TNETV107X_LPSC_SYSTEM 36 -#define TNETV107X_LPSC_IMCOP 37 -#define TNETV107X_LPSC_SPARE 38 -#define TNETV107X_LPSC_SDIO1 39 -#define TNETV107X_LPSC_USB1 40 -#define TNETV107X_LPSC_USBSS 41 -#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42 -#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43 -#define TNETV107X_LPSC_MAX 44 - /* PSC register offsets */ #define EPCPR 0x070 #define PTCMD 0x120 diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index ce402cd21fa0..d4b4aa87964f 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -23,14 +23,6 @@ #define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) #define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) -#define TNETV107X_UART0_BASE 0x08108100 -#define TNETV107X_UART1_BASE 0x08088400 -#define TNETV107X_UART2_BASE 0x08108300 - -#define TNETV107X_UART0_VIRT IOMEM(0xfee08100) -#define TNETV107X_UART1_VIRT IOMEM(0xfed88400) -#define TNETV107X_UART2_VIRT IOMEM(0xfee08300) - /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c #define UART_DM646X_SCR 0x10 diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h deleted file mode 100644 index 494fcf5ccfe1..000000000000 --- a/arch/arm/mach-davinci/include/mach/tnetv107x.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Texas Instruments TNETV107X SoC Specific Defines - * - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H -#define __ASM_ARCH_DAVINCI_TNETV107X_H - -#include <asm/sizes.h> - -#define TNETV107X_DDR_BASE 0x80000000 - -/* - * Fixed mapping for early init starts here. If low-level debug is enabled, - * this area also gets mapped via io_pg_offset and io_phys by the boot code. - * To fit in with the io_pg_offset calculation, the io base address selected - * here _must_ be a multiple of 2^20. - */ -#define TNETV107X_IO_BASE 0x08000000 -#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M) - -#define TNETV107X_N_GPIO 65 - -#ifndef __ASSEMBLY__ - -#include <linux/serial_8250.h> -#include <linux/input/matrix_keypad.h> -#include <linux/mfd/ti_ssp.h> -#include <linux/reboot.h> - -#include <linux/platform_data/mmc-davinci.h> -#include <linux/platform_data/mtd-davinci.h> -#include <mach/serial.h> - -struct tnetv107x_device_info { - struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ - struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ - struct matrix_keypad_platform_data *keypad_config; - struct ti_ssp_data *ssp_config; -}; - -extern struct platform_device tnetv107x_wdt_device; -extern struct platform_device tnetv107x_serial_device[]; - -extern void tnetv107x_init(void); -extern void tnetv107x_devices_init(struct tnetv107x_device_info *); -extern void tnetv107x_irq_init(void); -void tnetv107x_restart(enum reboot_mode mode, const char *cmd); - -#endif - -#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */ diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index f49c2916aa3a..8fb97b93b6bb 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -68,9 +68,6 @@ static inline void set_uart_info(u32 phys) #define DEBUG_LL_DA8XX(machine, port) \ _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE) -#define DEBUG_LL_TNETV107X(machine, port) \ - _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE) - static inline void __arch_decomp_setup(unsigned long arch_id) { /* @@ -94,9 +91,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_DA8XX(davinci_da850_evm, 2); DEBUG_LL_DA8XX(mityomapl138, 1); DEBUG_LL_DA8XX(omapl138_hawkboard, 2); - - /* TNETV107x boards */ - DEBUG_LL_TNETV107X(tnetv107x, 1); } while (0); } diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c deleted file mode 100644 index f4d7fbb24b3b..000000000000 --- a/arch/arm/mach-davinci/tnetv107x.c +++ /dev/null @@ -1,766 +0,0 @@ -/* - * Texas Instruments TNETV107X SoC Support - * - * Copyright (C) 2010 Texas Instruments - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/platform_device.h> -#include <linux/reboot.h> - -#include <asm/mach/map.h> - -#include <mach/common.h> -#include <mach/time.h> -#include <mach/cputype.h> -#include <mach/psc.h> -#include <mach/cp_intc.h> -#include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/tnetv107x.h> -#include <mach/gpio-davinci.h> - -#include "clock.h" -#include "mux.h" - -/* Base addresses for on-chip devices */ -#define TNETV107X_INTC_BASE 0x03000000 -#define TNETV107X_TIMER0_BASE 0x08086500 -#define TNETV107X_TIMER1_BASE 0x08086600 -#define TNETV107X_CHIP_CFG_BASE 0x08087000 -#define TNETV107X_GPIO_BASE 0x08088000 -#define TNETV107X_CLOCK_CONTROL_BASE 0x0808a000 -#define TNETV107X_PSC_BASE 0x0808b000 - -/* Reference clock frequencies */ -#define OSC_FREQ_ONCHIP (24000 * 1000) -#define OSC_FREQ_OFFCHIP_SYS (25000 * 1000) -#define OSC_FREQ_OFFCHIP_ETH (25000 * 1000) -#define OSC_FREQ_OFFCHIP_TDM (19200 * 1000) - -#define N_PLLS 3 - -/* Clock Control Registers */ -struct clk_ctrl_regs { - u32 pll_bypass; - u32 _reserved0; - u32 gem_lrst; - u32 _reserved1; - u32 pll_unlock_stat; - u32 sys_unlock; - u32 eth_unlock; - u32 tdm_unlock; -}; - -/* SSPLL Registers */ -struct sspll_regs { - u32 modes; - u32 post_div; - u32 pre_div; - u32 mult_factor; - u32 divider_range; - u32 bw_divider; - u32 spr_amount; - u32 spr_rate_div; - u32 diag; -}; - -/* Watchdog Timer Registers */ -struct wdt_regs { - u32 kick_lock; - u32 kick; - u32 change_lock; - u32 change ; - u32 disable_lock; - u32 disable; - u32 prescale_lock; - u32 prescale; -}; - -static struct clk_ctrl_regs __iomem *clk_ctrl_regs; - -static struct sspll_regs __iomem *sspll_regs[N_PLLS]; -static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 }; - -/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */ -static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) }; - -/* offchip (external) reference clock frequencies */ -static u32 pll_ext_freq[] = { - OSC_FREQ_OFFCHIP_SYS, - OSC_FREQ_OFFCHIP_TDM, - OSC_FREQ_OFFCHIP_ETH -}; - -/* PSC control registers */ -static u32 psc_regs[] = { TNETV107X_PSC_BASE }; - -/* Host map for interrupt controller */ -static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; - -static unsigned long clk_sspll_recalc(struct clk *clk); - -/* Level 1 - the PLLs */ -#define define_pll_clk(cname, pll, divmask, base) \ - static struct pll_data pll_##cname##_data = { \ - .num = pll, \ - .div_ratio_mask = divmask, \ - .phys_base = base + \ - TNETV107X_CLOCK_CONTROL_BASE, \ - }; \ - static struct clk pll_##cname##_clk = { \ - .name = "pll_" #cname "_clk", \ - .pll_data = &pll_##cname##_data, \ - .flags = CLK_PLL, \ - .recalc = clk_sspll_recalc, \ - } - -define_pll_clk(sys, 0, 0x1ff, 0x600); -define_pll_clk(tdm, 1, 0x0ff, 0x200); -define_pll_clk(eth, 2, 0x0ff, 0x400); - -/* Level 2 - divided outputs from the PLLs */ -#define define_pll_div_clk(pll, cname, div) \ - static struct clk pll##_##cname##_clk = { \ - .name = #pll "_" #cname "_clk", \ - .parent = &pll_##pll##_clk, \ - .flags = CLK_PLL, \ - .div_reg = PLLDIV##div, \ - .set_rate = davinci_set_sysclk_rate, \ - } - -define_pll_div_clk(sys, arm1176, 1); -define_pll_div_clk(sys, dsp, 2); -define_pll_div_clk(sys, ddr, 3); -define_pll_div_clk(sys, full, 4); -define_pll_div_clk(sys, lcd, 5); -define_pll_div_clk(sys, vlynq_ref, 6); -define_pll_div_clk(sys, tsc, 7); -define_pll_div_clk(sys, half, 8); - -define_pll_div_clk(eth, 5mhz, 1); -define_pll_div_clk(eth, 50mhz, 2); -define_pll_div_clk(eth, 125mhz, 3); -define_pll_div_clk(eth, 250mhz, 4); -define_pll_div_clk(eth, 25mhz, 5); - -define_pll_div_clk(tdm, 0, 1); -define_pll_div_clk(tdm, extra, 2); -define_pll_div_clk(tdm, 1, 3); - - -/* Level 3 - LPSC gated clocks */ -#define __lpsc_clk(cname, _parent, mod, flg) \ - static struct clk clk_##cname = { \ - .name = #cname, \ - .parent = &_parent, \ - .lpsc = TNETV107X_LPSC_##mod,\ - .flags = flg, \ - } - -#define lpsc_clk_enabled(cname, parent, mod) \ - __lpsc_clk(cname, parent, mod, ALWAYS_ENABLED) - -#define lpsc_clk(cname, parent, mod) \ - __lpsc_clk(cname, parent, mod, 0) - -lpsc_clk_enabled(arm, sys_arm1176_clk, ARM); -lpsc_clk_enabled(gem, sys_dsp_clk, GEM); -lpsc_clk_enabled(ddr2_phy, sys_ddr_clk, DDR2_PHY); -lpsc_clk_enabled(tpcc, sys_full_clk, TPCC); -lpsc_clk_enabled(tptc0, sys_full_clk, TPTC0); -lpsc_clk_enabled(tptc1, sys_full_clk, TPTC1); -lpsc_clk_enabled(ram, sys_full_clk, RAM); -lpsc_clk_enabled(aemif, sys_full_clk, AEMIF); -lpsc_clk_enabled(chipcfg, sys_half_clk, CHIP_CFG); -lpsc_clk_enabled(rom, sys_half_clk, ROM); -lpsc_clk_enabled(secctl, sys_half_clk, SECCTL); -lpsc_clk_enabled(keymgr, sys_half_clk, KEYMGR); -lpsc_clk_enabled(gpio, sys_half_clk, GPIO); -lpsc_clk_enabled(debugss, sys_half_clk, DEBUGSS); -lpsc_clk_enabled(system, sys_half_clk, SYSTEM); -lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); -lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); -lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); -lpsc_clk_enabled(timer1, sys_half_clk, TIMER1); - -lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); -lpsc_clk(ethss, eth_125mhz_clk, ETHSS); -lpsc_clk(tsc, sys_tsc_clk, TSC); -lpsc_clk(uart0, sys_half_clk, UART0); -lpsc_clk(uart1, sys_half_clk, UART1); -lpsc_clk(uart2, sys_half_clk, UART2); -lpsc_clk(pktsec, sys_half_clk, PKTSEC); -lpsc_clk(keypad, sys_half_clk, KEYPAD); -lpsc_clk(mdio, sys_half_clk, MDIO); -lpsc_clk(sdio0, sys_half_clk, SDIO0); -lpsc_clk(sdio1, sys_half_clk, SDIO1); -lpsc_clk(timer0, sys_half_clk, TIMER0); -lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); -lpsc_clk(ssp, sys_half_clk, SSP); -lpsc_clk(tdm0, tdm_0_clk, TDM0); -lpsc_clk(tdm1, tdm_1_clk, TDM1); -lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); -lpsc_clk(mcdma, sys_half_clk, MCDMA); -lpsc_clk(usbss, sys_half_clk, USBSS); -lpsc_clk(usb0, clk_usbss, USB0); -lpsc_clk(usb1, clk_usbss, USB1); -lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); -lpsc_clk(imcop, sys_dsp_clk, IMCOP); -lpsc_clk(spare, sys_half_clk, SPARE); - -/* LCD needs a full power down to clear controller state */ -__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE); - - -/* Level 4 - leaf clocks for LPSC modules shared across drivers */ -static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec }; -static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec }; - -static struct clk_lookup clks[] = { - CLK(NULL, "pll_sys_clk", &pll_sys_clk), - CLK(NULL, "pll_eth_clk", &pll_eth_clk), - CLK(NULL, "pll_tdm_clk", &pll_tdm_clk), - CLK(NULL, "sys_arm1176_clk", &sys_arm1176_clk), - CLK(NULL, "sys_dsp_clk", &sys_dsp_clk), - CLK(NULL, "sys_ddr_clk", &sys_ddr_clk), - CLK(NULL, "sys_full_clk", &sys_full_clk), - CLK(NULL, "sys_lcd_clk", &sys_lcd_clk), - CLK(NULL, "sys_vlynq_ref_clk", &sys_vlynq_ref_clk), - CLK(NULL, "sys_tsc_clk", &sys_tsc_clk), - CLK(NULL, "sys_half_clk", &sys_half_clk), - CLK(NULL, "eth_5mhz_clk", ð_5mhz_clk), - CLK(NULL, "eth_50mhz_clk", ð_50mhz_clk), - CLK(NULL, "eth_125mhz_clk", ð_125mhz_clk), - CLK(NULL, "eth_250mhz_clk", ð_250mhz_clk), - CLK(NULL, "eth_25mhz_clk", ð_25mhz_clk), - CLK(NULL, "tdm_0_clk", &tdm_0_clk), - CLK(NULL, "tdm_extra_clk", &tdm_extra_clk), - CLK(NULL, "tdm_1_clk", &tdm_1_clk), - CLK(NULL, "clk_arm", &clk_arm), - CLK(NULL, "clk_gem", &clk_gem), - CLK(NULL, "clk_ddr2_phy", &clk_ddr2_phy), - CLK(NULL, "clk_tpcc", &clk_tpcc), - CLK(NULL, "clk_tptc0", &clk_tptc0), - CLK(NULL, "clk_tptc1", &clk_tptc1), - CLK(NULL, "clk_ram", &clk_ram), - CLK(NULL, "clk_mbx_lite", &clk_mbx_lite), - CLK("tnetv107x-fb.0", NULL, &clk_lcd), - CLK(NULL, "clk_ethss", &clk_ethss), - CLK(NULL, "aemif", &clk_aemif), - CLK(NULL, "clk_chipcfg", &clk_chipcfg), - CLK("tnetv107x-ts.0", NULL, &clk_tsc), - CLK(NULL, "clk_rom", &clk_rom), - CLK("serial8250.2", NULL, &clk_uart2), - CLK(NULL, "clk_pktsec", &clk_pktsec), - CLK("tnetv107x-rng.0", NULL, &clk_rng), - CLK("tnetv107x-pka.0", NULL, &clk_pka), - CLK(NULL, "clk_secctl", &clk_secctl), - CLK(NULL, "clk_keymgr", &clk_keymgr), - CLK("tnetv107x-keypad.0", NULL, &clk_keypad), - CLK(NULL, "clk_gpio", &clk_gpio), - CLK(NULL, "clk_mdio", &clk_mdio), - CLK("dm6441-mmc.0", NULL, &clk_sdio0), - CLK("serial8250.0", NULL, &clk_uart0), - CLK("serial8250.1", NULL, &clk_uart1), - CLK(NULL, "timer0", &clk_timer0), - CLK(NULL, "timer1", &clk_timer1), - CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), - CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp), - CLK("ti-ssp", NULL, &clk_ssp), - CLK(NULL, "clk_tdm0", &clk_tdm0), - CLK(NULL, "clk_vlynq", &clk_vlynq), - CLK(NULL, "clk_mcdma", &clk_mcdma), - CLK(NULL, "clk_usbss", &clk_usbss), - CLK(NULL, "clk_usb0", &clk_usb0), - CLK(NULL, "clk_usb1", &clk_usb1), - CLK(NULL, "clk_tdm1", &clk_tdm1), - CLK(NULL, "clk_debugss", &clk_debugss), - CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), - CLK(NULL, "clk_system", &clk_system), - CLK(NULL, "clk_imcop", &clk_imcop), - CLK(NULL, "clk_spare", &clk_spare), - CLK("dm6441-mmc.1", NULL, &clk_sdio1), - CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), - CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), - CLK(NULL, NULL, NULL), -}; - -static const struct mux_config pins[] = { -#ifdef CONFIG_DAVINCI_MUX - MUX_CFG(TNETV107X, ASR_A00, 0, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO32, 0, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A01, 0, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO33, 0, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A02, 0, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO34, 0, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A03, 0, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO35, 0, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A04, 0, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO36, 0, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A05, 0, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO37, 0, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A06, 1, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO38, 1, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A07, 1, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO39, 1, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A08, 1, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO40, 1, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A09, 1, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO41, 1, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A10, 1, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO42, 1, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A11, 1, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, BOOT_STRP_0, 1, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A12, 2, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, BOOT_STRP_1, 2, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A13, 2, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO43, 2, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A14, 2, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO44, 2, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A15, 2, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO45, 2, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A16, 2, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO46, 2, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A17, 2, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO47, 2, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_A18, 3, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO48, 3, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_DATA3_0, 3, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A19, 3, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO49, 3, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_DATA2_0, 3, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A20, 3, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO50, 3, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_DATA1_0, 3, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A21, 3, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO51, 3, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_DATA0_0, 3, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A22, 3, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO52, 3, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_CMD_0, 3, 20, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_A23, 3, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO53, 3, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO1_CLK_0, 3, 25, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_BA_1, 4, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO54, 4, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SYS_PLL_CLK, 4, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_CS0, 4, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ASR_CS1, 4, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ASR_CS2, 4, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM_PLL_CLK, 4, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_CS3, 4, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ETH_PHY_CLK, 4, 20, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, ASR_D00, 4, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO55, 4, 25, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D01, 5, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO56, 5, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D02, 5, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO57, 5, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D03, 5, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO58, 5, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D04, 5, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO59_0, 5, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D05, 5, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO60_0, 5, 20, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D06, 5, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO61_0, 5, 25, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D07, 6, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO62_0, 6, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D08, 6, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO63_0, 6, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D09, 6, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO64_0, 6, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D10, 6, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_DATA3_1, 6, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D11, 6, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_DATA2_1, 6, 20, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D12, 6, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_DATA1_1, 6, 25, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D13, 7, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_DATA0_1, 7, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D14, 7, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_CMD_1, 7, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_D15, 7, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SDIO1_CLK_1, 7, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_OE, 7, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, BOOT_STRP_2, 7, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_RNW, 7, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO29_0, 7, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_WAIT, 7, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO30_0, 7, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_WE, 8, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, BOOT_STRP_3, 8, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, ASR_WE_DQM0, 8, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO31, 8, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD17_0, 8, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, ASR_WE_DQM1, 8, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ASR_BA0_0, 8, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, VLYNQ_CLK, 9, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO14, 9, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD19_0, 9, 0, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, VLYNQ_RXD0, 9, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO15, 9, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD20_0, 9, 5, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, VLYNQ_RXD1, 9, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO16, 9, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD21_0, 9, 10, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, VLYNQ_TXD0, 9, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO17, 9, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD22_0, 9, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, VLYNQ_TXD1, 9, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO18, 9, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD23_0, 9, 20, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, SDIO0_CLK, 10, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO19, 10, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_CMD, 10, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO20, 10, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_DATA0, 10, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO21, 10, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_DATA1, 10, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO22, 10, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_DATA2, 10, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO23, 10, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SDIO0_DATA3, 10, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO24, 10, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, EMU0, 11, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, EMU1, 11, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, RTCK, 12, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TRST_N, 12, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TCK, 12, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDI, 12, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDO, 12, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TMS, 12, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM1_CLK, 13, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM1_RX, 13, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM1_TX, 13, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM1_FS, 13, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R0, 14, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R1, 14, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R2, 14, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R3, 14, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R4, 14, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R5, 14, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_R6, 15, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO12, 15, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, KEYPAD_R7, 15, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO10, 15, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, KEYPAD_C0, 15, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C1, 15, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C2, 15, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C3, 15, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C4, 16, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C5, 16, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, KEYPAD_C6, 16, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO13, 16, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, TEST_CLK_IN, 16, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, KEYPAD_C7, 16, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO11, 16, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, SSP0_0, 17, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SCC_DCLK, 17, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD20_1, 17, 0, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP0_1, 17, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SCC_CS_N, 17, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD21_1, 17, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP0_2, 17, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SCC_D, 17, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD22_1, 17, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP0_3, 17, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, SCC_RESETN, 17, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, LCD_PD23_1, 17, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP1_0, 18, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO25, 18, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, UART2_CTS, 18, 0, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP1_1, 18, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO26, 18, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, UART2_RD, 18, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP1_2, 18, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO27, 18, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, UART2_RTS, 18, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, SSP1_3, 18, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO28, 18, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, UART2_TD, 18, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, UART0_CTS, 19, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART0_RD, 19, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART0_RTS, 19, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART0_TD, 19, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART1_RD, 19, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, UART1_TD, 19, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_AC_NCS, 20, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_HSYNC_RNW, 20, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_VSYNC_A0, 20, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_MCLK, 20, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD16_0, 20, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PCLK_E, 20, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD00, 20, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD01, 21, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD02, 21, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD03, 21, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD04, 21, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD05, 21, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD06, 21, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD07, 22, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD08, 22, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO59_1, 22, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD09, 22, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO60_1, 22, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD10, 22, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, ASR_BA0_1, 22, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, GPIO61_1, 22, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD11, 22, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO62_1, 22, 20, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD12, 22, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO63_1, 22, 25, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD13, 23, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO64_1, 23, 0, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD14, 23, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO29_1, 23, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, LCD_PD15, 23, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO30_1, 23, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, EINT0, 24, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO08, 24, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, EINT1, 24, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, GPIO09, 24, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, GPIO00, 24, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD20_2, 24, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, TDM_CLK_IN_2, 24, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO01, 24, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD21_2, 24, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, 24M_CLK_OUT_1, 24, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO02, 24, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD22_2, 24, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, GPIO03, 24, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD23_2, 24, 25, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, GPIO04, 25, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD16_1, 25, 0, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, USB0_RXERR, 25, 0, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO05, 25, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD17_1, 25, 5, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, TDM_CLK_IN_1, 25, 5, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO06, 25, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD18, 25, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, 24M_CLK_OUT_2, 25, 10, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, GPIO07, 25, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, LCD_PD19_1, 25, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, USB1_RXERR, 25, 15, 0x1f, 0x0c, false) - MUX_CFG(TNETV107X, ETH_PLL_CLK, 25, 15, 0x1f, 0x1c, false) - MUX_CFG(TNETV107X, MDIO, 26, 0, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, MDC, 26, 5, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, AIC_MUTE_STAT_N, 26, 10, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM0_CLK, 26, 10, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, AIC_HNS_EN_N, 26, 15, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM0_FS, 26, 15, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N, 26, 20, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM0_TX, 26, 20, 0x1f, 0x04, false) - MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N, 26, 25, 0x1f, 0x00, false) - MUX_CFG(TNETV107X, TDM0_RX, 26, 25, 0x1f, 0x04, false) -#endif -}; - -/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ -static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = { - /* fill in default priority 7 */ - [0 ... (TNETV107X_N_CP_INTC_IRQ - 1)] = 7, - /* now override as needed, e.g. [xxx] = 5 */ -}; - -/* Contents of JTAG ID register used to identify exact cpu type */ -static struct davinci_id ids[] = { - { - .variant = 0x0, - .part_no = 0xb8a1, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_TNETV107X, - .name = "tnetv107x rev 1.0", - }, - { - .variant = 0x1, - .part_no = 0xb8a1, - .manufacturer = 0x017, - .cpu_id = DAVINCI_CPU_ID_TNETV107X, - .name = "tnetv107x rev 1.1/1.2", - }, -}; - -static struct davinci_timer_instance timer_instance[2] = { - { - .base = TNETV107X_TIMER0_BASE, - .bottom_irq = IRQ_TNETV107X_TIMER_0_TINT12, - .top_irq = IRQ_TNETV107X_TIMER_0_TINT34, - }, - { - .base = TNETV107X_TIMER1_BASE, - .bottom_irq = IRQ_TNETV107X_TIMER_1_TINT12, - .top_irq = IRQ_TNETV107X_TIMER_1_TINT34, - }, -}; - -static struct davinci_timer_info timer_info = { - .timers = timer_instance, - .clockevent_id = T0_BOT, - .clocksource_id = T0_TOP, -}; - -/* - * TNETV107X platforms do not use the static mappings from Davinci - * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses, - * and changing IO_PHYS would break away from existing Davinci SOCs. - * - * The primary impact of the current model is that IO_ADDRESS() is not to be - * used to map registers on TNETV107X. - * - * 1. The first chunk is for INTC: This needs to be mapped in via iotable - * because ioremap() does not seem to be operational at the time when - * irqs are initialized. Without this, consistent dma init bombs. - * - * 2. The second chunk maps in register areas that need to be populated into - * davinci_soc_info. Note that alignment restrictions come into play if - * low-level debug is enabled (see note in <mach/tnetv107x.h>). - */ -static struct map_desc io_desc[] = { - { /* INTC */ - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(TNETV107X_INTC_BASE), - .length = SZ_16K, - .type = MT_DEVICE - }, - { /* Most of the rest */ - .virtual = TNETV107X_IO_VIRT, - .pfn = __phys_to_pfn(TNETV107X_IO_BASE), - .length = IO_SIZE - SZ_1M, - .type = MT_DEVICE - }, -}; - -static unsigned long clk_sspll_recalc(struct clk *clk) -{ - int pll; - unsigned long mult = 0, prediv = 1, postdiv = 1; - unsigned long ref = OSC_FREQ_ONCHIP, ret; - u32 tmp; - - if (WARN_ON(!clk->pll_data)) - return clk->rate; - - if (!clk_ctrl_regs) { - void __iomem *tmp; - - tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K); - - if (WARN(!tmp, "failed ioremap for clock control regs\n")) - return clk->parent ? clk->parent->rate : 0; - - for (pll = 0; pll < N_PLLS; pll++) - sspll_regs[pll] = tmp + sspll_regs_base[pll]; - - clk_ctrl_regs = tmp; - } - - pll = clk->pll_data->num; - - tmp = __raw_readl(&clk_ctrl_regs->pll_bypass); - if (!(tmp & bypass_mask[pll])) { - mult = __raw_readl(&sspll_regs[pll]->mult_factor); - prediv = __raw_readl(&sspll_regs[pll]->pre_div) + 1; - postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1; - } - - tmp = __raw_readl(clk->pll_data->base + PLLCTL); - if (tmp & PLLCTL_CLKMODE) - ref = pll_ext_freq[pll]; - - clk->pll_data->input_rate = ref; - - tmp = __raw_readl(clk->pll_data->base + PLLCTL); - if (!(tmp & PLLCTL_PLLEN)) - return ref; - - ret = ref; - if (mult) - ret += ((unsigned long long)ref * mult) / 256; - - ret /= (prediv * postdiv); - - return ret; -} - -static void tnetv107x_watchdog_reset(struct platform_device *pdev) -{ - struct wdt_regs __iomem *regs; - - regs = ioremap(pdev->resource[0].start, SZ_4K); - - /* disable watchdog */ - __raw_writel(0x7777, ®s->disable_lock); - __raw_writel(0xcccc, ®s->disable_lock); - __raw_writel(0xdddd, ®s->disable_lock); - __raw_writel(0, ®s->disable); - - /* program prescale */ - __raw_writel(0x5a5a, ®s->prescale_lock); - __raw_writel(0xa5a5, ®s->prescale_lock); - __raw_writel(0, ®s->prescale); - - /* program countdown */ - __raw_writel(0x6666, ®s->change_lock); - __raw_writel(0xbbbb, ®s->change_lock); - __raw_writel(1, ®s->change); - - /* enable watchdog */ - __raw_writel(0x7777, ®s->disable_lock); - __raw_writel(0xcccc, ®s->disable_lock); - __raw_writel(0xdddd, ®s->disable_lock); - __raw_writel(1, ®s->disable); - - /* kick */ - __raw_writel(0x5555, ®s->kick_lock); - __raw_writel(0xaaaa, ®s->kick_lock); - __raw_writel(1, ®s->kick); -} - -void tnetv107x_restart(enum reboot_mode mode, const char *cmd) -{ - tnetv107x_watchdog_reset(&tnetv107x_wdt_device); -} - -static struct davinci_soc_info tnetv107x_soc_info = { - .io_desc = io_desc, - .io_desc_num = ARRAY_SIZE(io_desc), - .ids = ids, - .ids_num = ARRAY_SIZE(ids), - .jtag_id_reg = TNETV107X_CHIP_CFG_BASE + 0x018, - .cpu_clks = clks, - .psc_bases = psc_regs, - .psc_bases_num = ARRAY_SIZE(psc_regs), - .pinmux_base = TNETV107X_CHIP_CFG_BASE + 0x150, - .pinmux_pins = pins, - .pinmux_pins_num = ARRAY_SIZE(pins), - .intc_type = DAVINCI_INTC_TYPE_CP_INTC, - .intc_base = TNETV107X_INTC_BASE, - .intc_irq_prios = irq_prios, - .intc_irq_num = TNETV107X_N_CP_INTC_IRQ, - .intc_host_map = intc_host_map, - .gpio_base = TNETV107X_GPIO_BASE, - .gpio_type = GPIO_TYPE_TNETV107X, - .gpio_num = TNETV107X_N_GPIO, - .timer_info = &timer_info, - .serial_dev = tnetv107x_serial_device, -}; - -void __init tnetv107x_init(void) -{ - davinci_common_init(&tnetv107x_soc_info); -} diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 0bc7cdf8cf46..d8c439c89ea9 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -20,18 +20,6 @@ config MACH_CM_A510 Say 'Y' here if you want your kernel to support the CompuLab CM-A510 Board. -config MACH_DOVE_DT - bool "Marvell Dove Flattened Device Tree" - select DOVE_CLK - select ORION_IRQCHIP - select ORION_TIMER - select REGULATOR - select REGULATOR_FIXED_VOLTAGE - select USE_OF - help - Say 'Y' here if you want your kernel to support the - Marvell Dove using flattened device tree. - endmenu endif diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index cbc5c0618788..b608a21919fb 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -2,5 +2,4 @@ obj-y += common.o obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o obj-$(CONFIG_PCI) += pcie.o obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o -obj-$(CONFIG_MACH_DOVE_DT) += board-dt.o obj-$(CONFIG_MACH_CM_A510) += cm-a510.o diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 41ffd433f709..5740296dc429 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,12 +1,15 @@ config ARCH_MXC bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 + select ARCH_HAS_CPUFREQ + select ARCH_HAS_OPP select ARCH_REQUIRE_GPIOLIB select ARM_CPU_SUSPEND if PM select CLKSRC_MMIO - select GENERIC_ALLOCATOR select GENERIC_IRQ_CHIP select PINCTRL + select PM_OPP if PM select SOC_BUS + select SRAM help Support for Freescale MXC/iMX-based family of processors @@ -116,8 +119,8 @@ config SOC_IMX35 select ARCH_MXC_IOMUX_V3 select HAVE_EPIT select MXC_AVIC + select PINCTRL_IMX35 select SMP_ON_UP if SMP - select PINCTRL config SOC_IMX5 bool @@ -768,53 +771,43 @@ config SOC_IMX50 config SOC_IMX53 bool "i.MX53 support" select HAVE_IMX_SRC - select IMX_HAVE_PLATFORM_IMX2_WDT select PINCTRL_IMX53 select SOC_IMX5 help This enables support for Freescale i.MX53 processor. -config SOC_IMX6Q - bool "i.MX6 Quad/DualLite support" - select ARCH_HAS_CPUFREQ - select ARCH_HAS_OPP +config SOC_IMX6 + bool select ARM_ERRATA_754322 - select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 select ARM_GIC - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP select HAVE_IMX_ANATOP select HAVE_IMX_GPC select HAVE_IMX_MMDC select HAVE_IMX_SRC select MFD_SYSCON - select MIGHT_HAVE_PCI - select PCI_DOMAINS if PCI - select PINCTRL_IMX6Q select PL310_ERRATA_588369 if CACHE_PL310 select PL310_ERRATA_727915 if CACHE_PL310 select PL310_ERRATA_769419 if CACHE_PL310 - select PM_OPP if PM + +config SOC_IMX6Q + bool "i.MX6 Quad/DualLite support" + select ARM_ERRATA_764369 if SMP + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if SMP + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI + select PINCTRL_IMX6Q + select SOC_IMX6 help This enables support for Freescale i.MX6 Quad processor. config SOC_IMX6SL bool "i.MX6 SoloLite support" - select ARM_ERRATA_754322 - select ARM_ERRATA_775420 - select ARM_GIC - select HAVE_IMX_ANATOP - select HAVE_IMX_GPC - select HAVE_IMX_MMDC - select HAVE_IMX_SRC - select MFD_SYSCON select PINCTRL_IMX6SL - select PL310_ERRATA_588369 if CACHE_PL310 - select PL310_ERRATA_727915 if CACHE_PL310 - select PL310_ERRATA_769419 if CACHE_PL310 + select SOC_IMX6 help This enables support for Freescale i.MX6 SoloLite processor. diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index ec419649320f..f4ed83032dd0 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o +obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o endif ifdef CONFIG_SND_IMX_SOC @@ -101,9 +102,11 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o -obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o -# i.MX6SL reuses i.MX6Q code -obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o +ifeq ($(CONFIG_SUSPEND),y) +AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o +endif +obj-$(CONFIG_SOC_IMX6) += pm-imx6.o # i.MX5 based machines obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index d7ed66091a2a..bdc2e4630a08 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -149,7 +149,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) clk_register_clkdev(clk[per1], "per", "imx-gpt.1"); clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2"); clk_register_clkdev(clk[per1], "per", "imx-gpt.2"); - clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0"); clk_register_clkdev(clk[per2], "per", "imx21-cspi.0"); clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0"); clk_register_clkdev(clk[per2], "per", "imx21-cspi.1"); diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 69858c78f40d..dc36e6c2f1da 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -265,14 +265,6 @@ int __init mx25_clocks_init(void) clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0"); clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1"); clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.0"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.1"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.2"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.3"); clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad"); clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc"); clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0"); diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index c6b40f386786..d2da8908b268 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -231,7 +231,6 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4"); clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5"); clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5"); - clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0"); clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0"); clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0"); clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1"); diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 19fca1fdc6fe..568ef0a4de84 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -266,8 +266,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1"); clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1"); clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2"); - clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0"); - clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1"); clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0"); clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1"); clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0"); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 4d677f442539..b0e7f9d2c245 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -437,12 +437,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); - clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); - clk_register_clkdev(clk[ahb], "ahb", NULL); - clk_register_clkdev(clk[cko1], "cko1", NULL); - clk_register_clkdev(clk[arm], NULL, "cpu0"); - clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); - clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); + clk_register_clkdev(clk[enet_ref], "enet_ref", NULL); if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index 4c86f3035205..f7073c0782fb 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -18,27 +18,43 @@ #include "clk.h" #include "common.h" -static const char const *step_sels[] = { "osc", "pll2_pfd2", }; -static const char const *pll1_sw_sels[] = { "pll1_sys", "step", }; -static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; -static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", }; -static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; -static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; -static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; -static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; -static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; -static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; -static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; -static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; -static const char const *perclk_sels[] = { "ipg", "osc", }; -static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; -static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; -static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; -static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; -static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; -static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; -static const char const *ecspi_sels[] = { "pll3_60m", "osc", }; -static const char const *uart_sels[] = { "pll3_80m", "osc", }; +#define CCSR 0xc +#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) +#define CACRR 0x10 +#define CDHIPR 0x48 +#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define ARM_WAIT_DIV_396M 2 +#define ARM_WAIT_DIV_792M 4 +#define ARM_WAIT_DIV_996M 6 + +#define PLL_ARM 0x0 +#define BM_PLL_ARM_DIV_SELECT (0x7f << 0) +#define BM_PLL_ARM_POWERDOWN (1 << 12) +#define BM_PLL_ARM_ENABLE (1 << 13) +#define BM_PLL_ARM_LOCK (1 << 31) +#define PLL_ARM_DIV_792M 66 + +static const char *step_sels[] = { "osc", "pll2_pfd2", }; +static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; +static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; +static const char *ocram_sels[] = { "periph", "ocram_alt_sels", }; +static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; +static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; +static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; +static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; +static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; +static const char *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; +static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; +static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; +static const char *perclk_sels[] = { "ipg", "osc", }; +static const char *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; +static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; +static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; +static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; +static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; +static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; +static const char *ecspi_sels[] = { "pll3_60m", "osc", }; +static const char *uart_sels[] = { "pll3_80m", "osc", }; static struct clk_div_table clk_enet_ref_table[] = { { .val = 0, .div = 20, }, @@ -65,6 +81,89 @@ static struct clk_div_table video_div_table[] = { static struct clk *clks[IMX6SL_CLK_END]; static struct clk_onecell_data clk_data; +static void __iomem *ccm_base; +static void __iomem *anatop_base; + +static const u32 clks_init_on[] __initconst = { + IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, +}; + +/* + * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken + * during WAIT mode entry process could cause cache memory + * corruption. + * + * Software workaround: + * To prevent this issue from occurring, software should ensure that the + * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before + * entering WAIT mode. + * + * This function will set the ARM clk to max value within the 12:5 limit. + * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz), + * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since + * the clk APIs can NOT be called in idle thread(may cause kernel schedule + * as there is sleep function in PLL wait function), so here we just slow + * down ARM to below freq according to previous freq: + * + * run mode wait mode + * 396MHz -> 132MHz; + * 792MHz -> 158.4MHz; + * 996MHz -> 142.3MHz; + */ +static int imx6sl_get_arm_divider_for_wait(void) +{ + if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { + return ARM_WAIT_DIV_396M; + } else { + if ((readl_relaxed(anatop_base + PLL_ARM) & + BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M) + return ARM_WAIT_DIV_792M; + else + return ARM_WAIT_DIV_996M; + } +} + +static void imx6sl_enable_pll_arm(bool enable) +{ + static u32 saved_pll_arm; + u32 val; + + if (enable) { + saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); + val |= BM_PLL_ARM_ENABLE; + val &= ~BM_PLL_ARM_POWERDOWN; + writel_relaxed(val, anatop_base + PLL_ARM); + while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) + ; + } else { + writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); + } +} + +void imx6sl_set_wait_clk(bool enter) +{ + static unsigned long saved_arm_div; + int arm_div_for_wait = imx6sl_get_arm_divider_for_wait(); + + /* + * According to hardware design, arm podf change need + * PLL1 clock enabled. + */ + if (arm_div_for_wait == ARM_WAIT_DIV_396M) + imx6sl_enable_pll_arm(true); + + if (enter) { + saved_arm_div = readl_relaxed(ccm_base + CACRR); + writel_relaxed(arm_div_for_wait, ccm_base + CACRR); + } else { + writel_relaxed(saved_arm_div, ccm_base + CACRR); + } + while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) + ; + + if (arm_div_for_wait == ARM_WAIT_DIV_396M) + imx6sl_enable_pll_arm(false); +} static void __init imx6sl_clocks_init(struct device_node *ccm_node) { @@ -72,6 +171,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) void __iomem *base; int irq; int i; + int ret; clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); @@ -80,6 +180,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); base = of_iomap(np, 0); WARN_ON(!base); + anatop_base = base; /* type name parent base div_mask */ clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); @@ -127,6 +228,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) np = ccm_node; base = of_iomap(np, 0); WARN_ON(!base); + ccm_base = base; /* Reuse imx6q pm code */ imx6q_pm_set_ccm_base(base); @@ -258,6 +360,19 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0"); clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0"); + /* Ensure the AHB clk is at 132MHz. */ + ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); + if (ret) + pr_warn("%s: failed to set AHB clock rate %d!\n", + __func__, ret); + + /* + * Make sure those always on clocks are enabled to maintain the correct + * usecount and enabling/disabling of parent PLLs. + */ + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + clk_prepare_enable(clks[clks_init_on[i]]); + if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index ecd66d8e20b6..22dc3ee21fd4 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -63,25 +63,25 @@ static void __iomem *anatop_base; static void __iomem *ccm_base; /* sources for multiplexer clocks, this is used multiple times */ -static const char const *fast_sels[] = { "firc", "fxosc", }; -static const char const *slow_sels[] = { "sirc_32k", "sxosc", }; -static const char const *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; -static const char const *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; -static const char const *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; -static const char const *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; -static const char const *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; -static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; -static const char const *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; -static const char const *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; -static const char const *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; -static const char const *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; -static const char const *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; -static const char const *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; -static const char const *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; -static const char const *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; +static const char *fast_sels[] = { "firc", "fxosc", }; +static const char *slow_sels[] = { "sirc_32k", "sxosc", }; +static const char *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; +static const char *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; +static const char *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; +static const char *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; +static const char *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; +static const char *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; +static const char *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; +static const char *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; +static const char *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; +static const char *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; +static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; +static const char *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; +static const char *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; +static const char *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; /* FTM counter clock source, not module clock */ -static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; -static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; +static const char *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; +static const char *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; static struct clk_div_table pll4_main_div_table[] = { { .val = 0, .div = 1 }, diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index baf439dc22d8..b5241ea76706 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -116,7 +116,6 @@ void imx_enable_cpu(int cpu, bool enable); void imx_set_cpu_jump(int cpu, void *jump_addr); u32 imx_get_cpu_arg(int cpu); void imx_set_cpu_arg(int cpu, u32 arg); -void v7_cpu_resume(void); #ifdef CONFIG_SMP void v7_secondary_startup(void); void imx_scu_map_io(void); @@ -139,13 +138,25 @@ void imx_anatop_init(void); void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -void imx6q_set_chicken_bit(void); +void imx6q_set_int_mem_clk_lpm(void); +void imx6sl_set_wait_clk(bool enter); void imx_cpu_die(unsigned int cpu); int imx_cpu_kill(unsigned int cpu); +#ifdef CONFIG_SUSPEND +void v7_cpu_resume(void); +void imx6_suspend(void __iomem *ocram_vbase); +#else +static inline void v7_cpu_resume(void) {} +static inline void imx6_suspend(void __iomem *ocram_vbase) {} +#endif + void imx6q_pm_init(void); +void imx6dl_pm_init(void); +void imx6sl_pm_init(void); void imx6q_pm_set_ccm_base(void __iomem *base); + #ifdef CONFIG_PM void imx5_pm_init(void); #else diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index 23ddfb693b2d..6bcae0479049 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -68,8 +68,8 @@ int __init imx6q_cpuidle_init(void) /* Need to enable SCU standby for entering WAIT modes */ imx_scu_standby_enable(); - /* Set chicken bit to get a reliable WAIT mode support */ - imx6q_set_chicken_bit(); + /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ + imx6q_set_int_mem_clk_lpm(); return cpuidle_register(&imx6q_cpuidle_driver, NULL); } diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c new file mode 100644 index 000000000000..d4b6b8171fa9 --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/cpuidle.h> +#include <linux/module.h> +#include <asm/cpuidle.h> +#include <asm/proc-fns.h> + +#include "common.h" +#include "cpuidle.h" + +static int imx6sl_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + imx6q_set_lpm(WAIT_UNCLOCKED); + /* + * Software workaround for ERR005311, see function + * description for details. + */ + imx6sl_set_wait_clk(true); + cpu_do_idle(); + imx6sl_set_wait_clk(false); + imx6q_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6sl_cpuidle_driver = { + .name = "imx6sl_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_TIMER_STOP, + .enter = imx6sl_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + }, + .state_count = 2, + .safe_state_index = 0, +}; + +int __init imx6sl_cpuidle_init(void) +{ + return cpuidle_register(&imx6sl_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h index 786f98ecc145..24e33670417c 100644 --- a/arch/arm/mach-imx/cpuidle.h +++ b/arch/arm/mach-imx/cpuidle.h @@ -13,6 +13,7 @@ #ifdef CONFIG_CPU_IDLE extern int imx5_cpuidle_init(void); extern int imx6q_cpuidle_init(void); +extern int imx6sl_cpuidle_init(void); #else static inline int imx5_cpuidle_init(void) { @@ -22,4 +23,8 @@ static inline int imx6q_cpuidle_init(void) { return 0; } +static inline int imx6sl_cpuidle_init(void) +{ + return 0; +} #endif diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h index 769563fdeaa0..61a114cddc39 100644 --- a/arch/arm/mach-imx/devices-imx25.h +++ b/arch/arm/mach-imx/devices-imx25.h @@ -83,7 +83,3 @@ extern const struct imx_spi_imx_data imx25_cspi_data[]; #define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) #define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) #define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) - -extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[]; -#define imx25_add_mxc_pwm(id) \ - imx_add_mxc_pwm(&imx25_mxc_pwm_data[id]) diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h index deee5baee88c..26389f35a2b2 100644 --- a/arch/arm/mach-imx/devices-imx51.h +++ b/arch/arm/mach-imx/devices-imx51.h @@ -57,10 +57,6 @@ extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[]; #define imx51_add_imx2_wdt(id) \ imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) -extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; -#define imx51_add_mxc_pwm(id) \ - imx_add_mxc_pwm(&imx51_mxc_pwm_data[id]) - extern const struct imx_imx_keypad_data imx51_imx_keypad_data; #define imx51_add_imx_keypad(pdata) \ imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig index 68c74fb0373c..2d260a5a307c 100644 --- a/arch/arm/mach-imx/devices/Kconfig +++ b/arch/arm/mach-imx/devices/Kconfig @@ -67,9 +67,6 @@ config IMX_HAVE_PLATFORM_MXC_MMC config IMX_HAVE_PLATFORM_MXC_NAND bool -config IMX_HAVE_PLATFORM_MXC_PWM - bool - config IMX_HAVE_PLATFORM_MXC_RNGA bool select ARCH_HAS_RNGA diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile index 67416fb1dc69..1cbc14cd80d1 100644 --- a/arch/arm/mach-imx/devices/Makefile +++ b/arch/arm/mach-imx/devices/Makefile @@ -23,7 +23,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h index c13b76b9f6b3..61352a80bb59 100644 --- a/arch/arm/mach-imx/devices/devices-common.h +++ b/arch/arm/mach-imx/devices/devices-common.h @@ -290,15 +290,6 @@ struct imx_pata_imx_data { struct platform_device *__init imx_add_pata_imx( const struct imx_pata_imx_data *data); -struct imx_mxc_pwm_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_pwm( - const struct imx_mxc_pwm_data *data); - /* mxc_rtc */ struct imx_mxc_rtc_data { const char *devid; diff --git a/arch/arm/mach-imx/devices/platform-mxc_pwm.c b/arch/arm/mach-imx/devices/platform-mxc_pwm.c deleted file mode 100644 index dcd289777687..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_pwm.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_PWM ## _hwid, \ - } -#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ - [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = - imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX25 -const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { -#define imx25_mxc_pwm_data_entry(_id, _hwid) \ - imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) - imx25_mxc_pwm_data_entry(0, 1), - imx25_mxc_pwm_data_entry(1, 2), - imx25_mxc_pwm_data_entry(2, 3), - imx25_mxc_pwm_data_entry(3, 4), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = - imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = { -#define imx51_mxc_pwm_data_entry(_id, _hwid) \ - imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K) - imx51_mxc_pwm_data_entry(0, 1), - imx51_mxc_pwm_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -struct platform_device *__init imx_add_mxc_pwm( - const struct imx_mxc_pwm_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("mxc_pwm", data->id, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index a3b0b04b45c9..abf43bb47eca 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -20,7 +20,9 @@ #ifndef __ASM_ARCH_MXC_HARDWARE_H__ #define __ASM_ARCH_MXC_HARDWARE_H__ +#ifndef __ASSEMBLY__ #include <asm/io.h> +#endif #include <asm/sizes.h> #define addr_in_module(addr, mod) \ diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 627f16f0e9d1..de5047c8a6c8 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -12,12 +12,7 @@ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/asm-offsets.h> -#include <asm/hardware/cache-l2x0.h> - .section ".text.head", "ax" - -#ifdef CONFIG_SMP diag_reg_offset: .word g_diag_reg - . @@ -34,38 +29,3 @@ ENTRY(v7_secondary_startup) set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) -#endif - -#ifdef CONFIG_ARM_CPU_SUSPEND -/* - * The following code must assume it is running from physical address - * where absolute virtual addresses to the data section have to be - * turned into relative ones. - */ - -#ifdef CONFIG_CACHE_L2X0 - .macro pl310_resume - adr r0, l2x0_saved_regs_offset - ldr r2, [r0] - add r2, r2, r0 - ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 - ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value - str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl - mov r1, #0x1 - str r1, [r0, #L2X0_CTRL] @ re-enable L2 - .endm - -l2x0_saved_regs_offset: - .word l2x0_saved_regs - . - -#else - .macro pl310_resume - .endm -#endif - -ENTRY(v7_cpu_resume) - bl v7_invalidate_l1 - pl310_resume - b cpu_resume -ENDPROC(v7_cpu_resume) -#endif diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 76e5db4fce35..e60456d85c9d 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -182,16 +182,83 @@ static void __init imx6q_enet_phy_init(void) static void __init imx6q_1588_init(void) { + struct device_node *np; + struct clk *ptp_clk; + struct clk *enet_ref; struct regmap *gpr; + u32 clksel; + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); + if (!np) { + pr_warn("%s: failed to find fec node\n", __func__); + return; + } + + ptp_clk = of_clk_get(np, 2); + if (IS_ERR(ptp_clk)) { + pr_warn("%s: failed to get ptp clock\n", __func__); + goto put_node; + } + + enet_ref = clk_get_sys(NULL, "enet_ref"); + if (IS_ERR(enet_ref)) { + pr_warn("%s: failed to get enet clock\n", __func__); + goto put_ptp_clk; + } + + /* + * If enet_ref from ANATOP/CCM is the PTP clock source, we need to + * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad + * (external OSC), and we need to clear the bit. + */ + clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP : + IMX6Q_GPR1_ENET_CLK_SEL_PAD; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_ENET_CLK_SEL_MASK, - IMX6Q_GPR1_ENET_CLK_SEL_ANATOP); + clksel); else pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); + clk_put(enet_ref); +put_ptp_clk: + clk_put(ptp_clk); +put_node: + of_node_put(np); +} + +static void __init imx6q_axi_init(void) +{ + struct regmap *gpr; + unsigned int mask; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + /* + * Enable the cacheable attribute of VPU and IPU + * AXI transactions. + */ + mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL | + IMX6Q_GPR4_VPU_RD_CACHE_SEL | + IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | + IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK | + IMX6Q_GPR4_IPU_WR_CACHE_CTL | + IMX6Q_GPR4_IPU_RD_CACHE_CTL; + regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask); + + /* Increase IPU read QoS priority */ + regmap_update_bits(gpr, IOMUXC_GPR6, + IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK | + IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK, + (0xf << 16) | (0x7 << 20)); + regmap_update_bits(gpr, IOMUXC_GPR7, + IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | + IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK, + (0xf << 16) | (0x7 << 20)); + } else { + pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + } } static void __init imx6q_init_machine(void) @@ -212,15 +279,18 @@ static void __init imx6q_init_machine(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); imx_anatop_init(); - imx6q_pm_init(); + cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); imx6q_1588_init(); + imx6q_axi_init(); } #define OCOTP_CFG3 0x440 #define OCOTP_CFG3_SPEED_SHIFT 16 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 +#define OCOTP_CFG3_SPEED_996MHZ 0x2 +#define OCOTP_CFG3_SPEED_852MHZ 0x1 -static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) +static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev) { struct device_node *np; void __iomem *base; @@ -238,11 +308,29 @@ static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) goto put_node; } + /* + * SPEED_GRADING[1:0] defines the max speed of ARM: + * 2b'11: 1200000000Hz; + * 2b'10: 996000000Hz; + * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. + * 2b'00: 792000000Hz; + * We need to set the max speed of ARM according to fuse map. + */ val = readl_relaxed(base + OCOTP_CFG3); val >>= OCOTP_CFG3_SPEED_SHIFT; - if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) + val &= 0x3; + + if (val != OCOTP_CFG3_SPEED_1P2GHZ) if (dev_pm_opp_disable(cpu_dev, 1200000000)) pr_warn("failed to disable 1.2 GHz OPP\n"); + if (val < OCOTP_CFG3_SPEED_996MHZ) + if (dev_pm_opp_disable(cpu_dev, 996000000)) + pr_warn("failed to disable 996 MHz OPP\n"); + if (cpu_is_imx6q()) { + if (val != OCOTP_CFG3_SPEED_852MHZ) + if (dev_pm_opp_disable(cpu_dev, 852000000)) + pr_warn("failed to disable 852 MHz OPP\n"); + } put_node: of_node_put(np); @@ -268,7 +356,7 @@ static void __init imx6q_opp_init(void) goto put_node; } - imx6q_opp_check_1p2ghz(cpu_dev); + imx6q_opp_check_speed_grading(cpu_dev); put_node: of_node_put(np); diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 0f4fd4c0ab8e..ad323385115c 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -17,6 +17,7 @@ #include <asm/mach/map.h> #include "common.h" +#include "cpuidle.h" static void __init imx6sl_fec_init(void) { @@ -39,6 +40,8 @@ static void __init imx6sl_init_late(void) /* imx6sl reuses imx6q cpufreq driver */ if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); + + imx6sl_cpuidle_init(); } static void __init imx6sl_init_machine(void) @@ -55,8 +58,7 @@ static void __init imx6sl_init_machine(void) imx6sl_fec_init(); imx_anatop_init(); - /* Reuse imx6q pm code */ - imx6q_pm_init(); + imx6sl_pm_init(); } static void __init imx6sl_init_irq(void) diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c new file mode 100644 index 000000000000..9392a8f4ef24 --- /dev/null +++ b/arch/arm/mach-imx/pm-imx6.c @@ -0,0 +1,551 @@ +/* + * Copyright 2011-2014 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/genalloc.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/regmap.h> +#include <linux/suspend.h> +#include <asm/cacheflush.h> +#include <asm/fncpy.h> +#include <asm/proc-fns.h> +#include <asm/suspend.h> +#include <asm/tlb.h> + +#include "common.h" +#include "hardware.h" + +#define CCR 0x0 +#define BM_CCR_WB_COUNT (0x7 << 16) +#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) +#define BM_CCR_RBC_EN (0x1 << 27) + +#define CLPCR 0x54 +#define BP_CLPCR_LPM 0 +#define BM_CLPCR_LPM (0x3 << 0) +#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) +#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define BM_CLPCR_SBYOS (0x1 << 6) +#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define BM_CLPCR_VSTBY (0x1 << 8) +#define BP_CLPCR_STBY_COUNT 9 +#define BM_CLPCR_STBY_COUNT (0x3 << 9) +#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) +#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) +#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) +#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) +#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) +#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) +#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) +#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) +#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) +#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) + +#define CGPR 0x64 +#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) + +#define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 +#define MX6_MAX_MMDC_IO_NUM 33 + +static void __iomem *ccm_base; +static void __iomem *suspend_ocram_base; +static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); + +/* + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx6_suspend code + * PM_INFO structure(imx6_cpu_pm_info) + * ======================== low address ======================= + */ + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx6_pm_socdata { + u32 cpu_type; + const char *mmdc_compat; + const char *src_compat; + const char *iomuxc_compat; + const char *gpc_compat; + const u32 mmdc_io_num; + const u32 *mmdc_io_offset; +}; + +static const u32 imx6q_mmdc_io_offset[] __initconst = { + 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ + 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ + 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ + 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ + 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ + 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ + 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ + 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x74c, /* GPR_ADDS */ +}; + +static const u32 imx6dl_mmdc_io_offset[] __initconst = { + 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ + 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ + 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */ + 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */ + 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */ + 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */ + 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */ + 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x74c, /* GPR_ADDS */ +}; + +static const u32 imx6sl_mmdc_io_offset[] __initconst = { + 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ + 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ + 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ +}; + +static const struct imx6_pm_socdata imx6q_pm_data __initconst = { + .cpu_type = MXC_CPU_IMX6Q, + .mmdc_compat = "fsl,imx6q-mmdc", + .src_compat = "fsl,imx6q-src", + .iomuxc_compat = "fsl,imx6q-iomuxc", + .gpc_compat = "fsl,imx6q-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), + .mmdc_io_offset = imx6q_mmdc_io_offset, +}; + +static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { + .cpu_type = MXC_CPU_IMX6DL, + .mmdc_compat = "fsl,imx6q-mmdc", + .src_compat = "fsl,imx6q-src", + .iomuxc_compat = "fsl,imx6dl-iomuxc", + .gpc_compat = "fsl,imx6q-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), + .mmdc_io_offset = imx6dl_mmdc_io_offset, +}; + +static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { + .cpu_type = MXC_CPU_IMX6SL, + .mmdc_compat = "fsl,imx6sl-mmdc", + .src_compat = "fsl,imx6sl-src", + .iomuxc_compat = "fsl,imx6sl-iomuxc", + .gpc_compat = "fsl,imx6sl-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), + .mmdc_io_offset = imx6sl_mmdc_io_offset, +}; + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly, + * otherwise, the suspend to ocram function will be broken! + */ +struct imx6_cpu_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 cpu_type; + u32 pm_info_size; /* Size of pm_info. */ + struct imx6_pm_base mmdc_base; + struct imx6_pm_base src_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base l2_base; + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +void imx6q_set_int_mem_clk_lpm(void) +{ + u32 val = readl_relaxed(ccm_base + CGPR); + + val |= BM_CGPR_INT_MEM_CLK_LPM; + writel_relaxed(val, ccm_base + CGPR); +} + +static void imx6q_enable_rbc(bool enable) +{ + u32 val; + + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + imx_gpc_mask_all(); + + /* configure RBC enable bit */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_EN; + val |= enable ? BM_CCR_RBC_EN : 0; + writel_relaxed(val, ccm_base + CCR); + + /* configure RBC count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_BYPASS_COUNT; + val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; + writel(val, ccm_base + CCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); + + /* restore GPC interrupt mask settings */ + imx_gpc_restore_all(); +} + +static void imx6q_enable_wb(bool enable) +{ + u32 val; + + /* configure well bias enable bit */ + val = readl_relaxed(ccm_base + CLPCR); + val &= ~BM_CLPCR_WB_PER_AT_LPM; + val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; + writel_relaxed(val, ccm_base + CLPCR); + + /* configure well bias count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_WB_COUNT; + val |= enable ? BM_CCR_WB_COUNT : 0; + writel_relaxed(val, ccm_base + CCR); +} + +int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) +{ + struct irq_data *iomuxc_irq_data = irq_get_irq_data(32); + u32 val = readl_relaxed(ccm_base + CLPCR); + + val &= ~BM_CLPCR_LPM; + switch (mode) { + case WAIT_CLOCKED: + break; + case WAIT_UNCLOCKED: + val |= 0x1 << BP_CLPCR_LPM; + val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; + break; + case STOP_POWER_ON: + val |= 0x2 << BP_CLPCR_LPM; + break; + case WAIT_UNCLOCKED_POWER_OFF: + val |= 0x1 << BP_CLPCR_LPM; + val &= ~BM_CLPCR_VSTBY; + val &= ~BM_CLPCR_SBYOS; + break; + case STOP_POWER_OFF: + val |= 0x2 << BP_CLPCR_LPM; + val |= 0x3 << BP_CLPCR_STBY_COUNT; + val |= BM_CLPCR_VSTBY; + val |= BM_CLPCR_SBYOS; + if (cpu_is_imx6sl()) { + val |= BM_CLPCR_BYPASS_PMIC_READY; + val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + } else { + val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + } + break; + default: + return -EINVAL; + } + + /* + * ERR007265: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #32 (IOMUX) to be always pending + * by setting IOMUX_GPR1_GINT. + * 2) Software should then unmask IRQ #32 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #32 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). + */ + imx_gpc_irq_unmask(iomuxc_irq_data); + writel_relaxed(val, ccm_base + CLPCR); + imx_gpc_irq_mask(iomuxc_irq_data); + + return 0; +} + +static int imx6q_suspend_finish(unsigned long val) +{ + if (!imx6_suspend_in_ocram_fn) { + cpu_do_idle(); + } else { + /* + * call low level suspend function in ocram, + * as we need to float DDR IO. + */ + local_flush_tlb_all(); + imx6_suspend_in_ocram_fn(suspend_ocram_base); + } + + return 0; +} + +static int imx6q_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_MEM: + imx6q_set_lpm(STOP_POWER_OFF); + imx6q_enable_wb(true); + /* + * For suspend into ocram, asm code already take care of + * RBC setting, so we do NOT need to do that here. + */ + if (!imx6_suspend_in_ocram_fn) + imx6q_enable_rbc(true); + imx_gpc_pre_suspend(); + imx_anatop_pre_suspend(); + imx_set_cpu_jump(0, v7_cpu_resume); + /* Zzz ... */ + cpu_suspend(0, imx6q_suspend_finish); + if (cpu_is_imx6q() || cpu_is_imx6dl()) + imx_smp_prepare(); + imx_anatop_post_resume(); + imx_gpc_post_resume(); + imx6q_enable_rbc(false); + imx6q_enable_wb(false); + imx6q_set_lpm(WAIT_CLOCKED); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct platform_suspend_ops imx6q_pm_ops = { + .enter = imx6q_pm_enter, + .valid = suspend_valid_only_mem, +}; + +void __init imx6q_pm_set_ccm_base(void __iomem *base) +{ + ccm_base = base; +} + +static int __init imx6_pm_get_base(struct imx6_pm_base *base, + const char *compat) +{ + struct device_node *node; + struct resource res; + int ret = 0; + + node = of_find_compatible_node(NULL, NULL, compat); + if (!node) { + ret = -ENODEV; + goto out; + } + + ret = of_address_to_resource(node, 0, &res); + if (ret) + goto put_node; + + base->pbase = res.start; + base->vbase = ioremap(res.start, resource_size(&res)); + if (!base->vbase) + ret = -ENOMEM; + +put_node: + of_node_put(node); +out: + return ret; +} + +static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) +{ + phys_addr_t ocram_pbase; + struct device_node *node; + struct platform_device *pdev; + struct imx6_cpu_pm_info *pm_info; + struct gen_pool *ocram_pool; + unsigned long ocram_base; + int i, ret = 0; + const u32 *mmdc_offset_array; + + suspend_set_ops(&imx6q_pm_ops); + + if (!socdata) { + pr_warn("%s: invalid argument!\n", __func__); + return -EINVAL; + } + + node = of_find_compatible_node(NULL, NULL, "mmio-sram"); + if (!node) { + pr_warn("%s: failed to find ocram node!\n", __func__); + return -ENODEV; + } + + pdev = of_find_device_by_node(node); + if (!pdev) { + pr_warn("%s: failed to find ocram device!\n", __func__); + ret = -ENODEV; + goto put_node; + } + + ocram_pool = dev_get_gen_pool(&pdev->dev); + if (!ocram_pool) { + pr_warn("%s: ocram pool unavailable!\n", __func__); + ret = -ENODEV; + goto put_node; + } + + ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); + if (!ocram_base) { + pr_warn("%s: unable to alloc ocram!\n", __func__); + ret = -ENOMEM; + goto put_node; + } + + ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); + + suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, + MX6Q_SUSPEND_OCRAM_SIZE, false); + + pm_info = suspend_ocram_base; + pm_info->pbase = ocram_pbase; + pm_info->resume_addr = virt_to_phys(v7_cpu_resume); + pm_info->pm_info_size = sizeof(*pm_info); + + /* + * ccm physical address is not used by asm code currently, + * so get ccm virtual address directly, as we already have + * it from ccm driver. + */ + pm_info->ccm_base.vbase = ccm_base; + + ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); + if (ret) { + pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); + goto put_node; + } + + ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); + if (ret) { + pr_warn("%s: failed to get src base %d!\n", __func__, ret); + goto src_map_failed; + } + + ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); + if (ret) { + pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); + goto iomuxc_map_failed; + } + + ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); + if (ret) { + pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); + goto gpc_map_failed; + } + + ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache"); + if (ret) { + pr_warn("%s: failed to get pl310-cache base %d!\n", + __func__, ret); + goto pl310_cache_map_failed; + } + + pm_info->cpu_type = socdata->cpu_type; + pm_info->mmdc_io_num = socdata->mmdc_io_num; + mmdc_offset_array = socdata->mmdc_io_offset; + + for (i = 0; i < pm_info->mmdc_io_num; i++) { + pm_info->mmdc_io_val[i][0] = + mmdc_offset_array[i]; + pm_info->mmdc_io_val[i][1] = + readl_relaxed(pm_info->iomuxc_base.vbase + + mmdc_offset_array[i]); + } + + imx6_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*pm_info), + &imx6_suspend, + MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); + + goto put_node; + +pl310_cache_map_failed: + iounmap(&pm_info->gpc_base.vbase); +gpc_map_failed: + iounmap(&pm_info->iomuxc_base.vbase); +iomuxc_map_failed: + iounmap(&pm_info->src_base.vbase); +src_map_failed: + iounmap(&pm_info->mmdc_base.vbase); +put_node: + of_node_put(node); + + return ret; +} + +static void __init imx6_pm_common_init(const struct imx6_pm_socdata + *socdata) +{ + struct regmap *gpr; + int ret; + + WARN_ON(!ccm_base); + + if (IS_ENABLED(CONFIG_SUSPEND)) { + ret = imx6q_suspend_init(socdata); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + } + + /* + * This is for SW workaround step #1 of ERR007265, see comments + * in imx6q_set_lpm for details of this errata. + * Force IOMUXC irq pending, so that the interrupt to GPC can be + * used to deassert dsm_request signal when the signal gets + * asserted unexpectedly. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, + IMX6Q_GPR1_GINT); +} + +void __init imx6q_pm_init(void) +{ + imx6_pm_common_init(&imx6q_pm_data); +} + +void __init imx6dl_pm_init(void) +{ + imx6_pm_common_init(&imx6dl_pm_data); +} + +void __init imx6sl_pm_init(void) +{ + imx6_pm_common_init(&imx6sl_pm_data); +} diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c deleted file mode 100644 index 29e3fe6a6669..000000000000 --- a/arch/arm/mach-imx/pm-imx6q.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright 2011-2013 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/mfd/syscon.h> -#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/regmap.h> -#include <linux/suspend.h> -#include <asm/cacheflush.h> -#include <asm/proc-fns.h> -#include <asm/suspend.h> -#include <asm/hardware/cache-l2x0.h> - -#include "common.h" -#include "hardware.h" - -#define CCR 0x0 -#define BM_CCR_WB_COUNT (0x7 << 16) -#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) -#define BM_CCR_RBC_EN (0x1 << 27) - -#define CLPCR 0x54 -#define BP_CLPCR_LPM 0 -#define BM_CLPCR_LPM (0x3 << 0) -#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) -#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define BM_CLPCR_SBYOS (0x1 << 6) -#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define BM_CLPCR_VSTBY (0x1 << 8) -#define BP_CLPCR_STBY_COUNT 9 -#define BM_CLPCR_STBY_COUNT (0x3 << 9) -#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) -#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) -#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) -#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) -#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) -#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) -#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) -#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) -#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) -#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) -#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) - -#define CGPR 0x64 -#define BM_CGPR_CHICKEN_BIT (0x1 << 17) - -static void __iomem *ccm_base; - -void imx6q_set_chicken_bit(void) -{ - u32 val = readl_relaxed(ccm_base + CGPR); - - val |= BM_CGPR_CHICKEN_BIT; - writel_relaxed(val, ccm_base + CGPR); -} - -static void imx6q_enable_rbc(bool enable) -{ - u32 val; - - /* - * need to mask all interrupts in GPC before - * operating RBC configurations - */ - imx_gpc_mask_all(); - - /* configure RBC enable bit */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_EN; - val |= enable ? BM_CCR_RBC_EN : 0; - writel_relaxed(val, ccm_base + CCR); - - /* configure RBC count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_BYPASS_COUNT; - val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; - writel(val, ccm_base + CCR); - - /* - * need to delay at least 2 cycles of CKIL(32K) - * due to hardware design requirement, which is - * ~61us, here we use 65us for safe - */ - udelay(65); - - /* restore GPC interrupt mask settings */ - imx_gpc_restore_all(); -} - -static void imx6q_enable_wb(bool enable) -{ - u32 val; - - /* configure well bias enable bit */ - val = readl_relaxed(ccm_base + CLPCR); - val &= ~BM_CLPCR_WB_PER_AT_LPM; - val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; - writel_relaxed(val, ccm_base + CLPCR); - - /* configure well bias count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_WB_COUNT; - val |= enable ? BM_CCR_WB_COUNT : 0; - writel_relaxed(val, ccm_base + CCR); -} - -int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) -{ - struct irq_data *iomuxc_irq_data = irq_get_irq_data(32); - u32 val = readl_relaxed(ccm_base + CLPCR); - - val &= ~BM_CLPCR_LPM; - switch (mode) { - case WAIT_CLOCKED: - break; - case WAIT_UNCLOCKED: - val |= 0x1 << BP_CLPCR_LPM; - val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; - break; - case STOP_POWER_ON: - val |= 0x2 << BP_CLPCR_LPM; - break; - case WAIT_UNCLOCKED_POWER_OFF: - val |= 0x1 << BP_CLPCR_LPM; - val &= ~BM_CLPCR_VSTBY; - val &= ~BM_CLPCR_SBYOS; - break; - case STOP_POWER_OFF: - val |= 0x2 << BP_CLPCR_LPM; - val |= 0x3 << BP_CLPCR_STBY_COUNT; - val |= BM_CLPCR_VSTBY; - val |= BM_CLPCR_SBYOS; - if (cpu_is_imx6sl()) { - val |= BM_CLPCR_BYPASS_PMIC_READY; - val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; - } else { - val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; - } - break; - default: - return -EINVAL; - } - - /* - * ERR007265: CCM: When improper low-power sequence is used, - * the SoC enters low power mode before the ARM core executes WFI. - * - * Software workaround: - * 1) Software should trigger IRQ #32 (IOMUX) to be always pending - * by setting IOMUX_GPR1_GINT. - * 2) Software should then unmask IRQ #32 in GPC before setting CCM - * Low-Power mode. - * 3) Software should mask IRQ #32 right after CCM Low-Power mode - * is set (set bits 0-1 of CCM_CLPCR). - */ - imx_gpc_irq_unmask(iomuxc_irq_data); - writel_relaxed(val, ccm_base + CLPCR); - imx_gpc_irq_mask(iomuxc_irq_data); - - return 0; -} - -static int imx6q_suspend_finish(unsigned long val) -{ - cpu_do_idle(); - return 0; -} - -static int imx6q_pm_enter(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_MEM: - imx6q_set_lpm(STOP_POWER_OFF); - imx6q_enable_wb(true); - imx6q_enable_rbc(true); - imx_gpc_pre_suspend(); - imx_anatop_pre_suspend(); - imx_set_cpu_jump(0, v7_cpu_resume); - /* Zzz ... */ - cpu_suspend(0, imx6q_suspend_finish); - if (cpu_is_imx6q() || cpu_is_imx6dl()) - imx_smp_prepare(); - imx_anatop_post_resume(); - imx_gpc_post_resume(); - imx6q_enable_rbc(false); - imx6q_enable_wb(false); - imx6q_set_lpm(WAIT_CLOCKED); - break; - default: - return -EINVAL; - } - - return 0; -} - -static const struct platform_suspend_ops imx6q_pm_ops = { - .enter = imx6q_pm_enter, - .valid = suspend_valid_only_mem, -}; - -void __init imx6q_pm_set_ccm_base(void __iomem *base) -{ - ccm_base = base; -} - -void __init imx6q_pm_init(void) -{ - struct regmap *gpr; - - WARN_ON(!ccm_base); - - /* - * This is for SW workaround step #1 of ERR007265, see comments - * in imx6q_set_lpm for details of this errata. - * Force IOMUXC irq pending, so that the interrupt to GPC can be - * used to deassert dsm_request signal when the signal gets - * asserted unexpectedly. - */ - gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); - if (!IS_ERR(gpr)) - regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, - IMX6Q_GPR1_GINT); - - - suspend_set_ops(&imx6q_pm_ops); -} diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S new file mode 100644 index 000000000000..20048ff05739 --- /dev/null +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -0,0 +1,361 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/linkage.h> +#include <asm/asm-offsets.h> +#include <asm/hardware/cache-l2x0.h> +#include "hardware.h" + +/* + * ==================== low level suspend ==================== + * + * Better to follow below rules to use ARM registers: + * r0: pm_info structure address; + * r1 ~ r4: for saving pm_info members; + * r5 ~ r10: free registers; + * r11: io base address. + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx6_suspend code + * PM_INFO structure(imx6_cpu_pm_info) + * ======================== low address ======================= + */ + +/* + * Below offsets are based on struct imx6_cpu_pm_info + * which defined in arch/arm/mach-imx/pm-imx6q.c, this + * structure contains necessary pm info for low level + * suspend related code. + */ +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_CPU_TYPE_OFFSET 0x8 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24 +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34 +#define PM_INFO_MX6Q_L2_P_OFFSET 0x38 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 + +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + + .align 3 + + .macro sync_l2_cache + + /* sync L2 cache to drain L2's buffers to DRAM. */ +#ifdef CONFIG_CACHE_L2X0 + ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + mov r6, #0x0 + str r6, [r11, #L2X0_CACHE_SYNC] +1: + ldr r6, [r11, #L2X0_CACHE_SYNC] + ands r6, r6, #0x1 + bne 1b +#endif + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +1: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r6, r6, #0x1 + bne 1b + + cmp r5, #0x0 + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + cmp r3, #MXC_CPU_IMX6SL + bne 4f + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +2: + ldr r6, [r11, r7] + ands r6, r6, #(1 << 31) + bne 2b + + /* reset FIFO a second time */ + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +3: + ldr r6, [r11, r7] + ands r6, r6, #(1 << 31) + bne 3b +4: + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r11, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 5b + + /* enable DDR auto power saving */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX6Q_MMDC_MAPSR] + + .endm + +ENTRY(imx6_suspend) + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET] + ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r6, =imx6_suspend + ldr r7, =resume + sub r7, r7, r6 + add r8, r1, r4 + add r9, r8, r7 + + /* + * make sure TLB contain the addr we want, + * as we will access them after MMDC IO floated. + */ + + ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r6, [r11, #0x0] + ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r6, [r11, #0x0] + + /* use r11 to store the IO address */ + ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + /* store physical resume addr and pm_info address. */ + str r9, [r11, #MX6Q_SRC_GPR1] + str r1, [r11, #MX6Q_SRC_GPR2] + + /* need to sync L2 cache before DSM. */ + sync_l2_cache + + ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + /* + * put DDR explicitly into self-refresh and + * disable automatic power savings. + */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r11, #MX6Q_MMDC_MAPSR] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r11, #MX6Q_MMDC_MAPSR] + +poll_dvfs_set: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq poll_dvfs_set + + ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 + /* i.MX6SL's last 3 IOs need special setting */ + cmp r3, #MXC_CPU_IMX6SL + subeq r7, r7, #0x3 +set_mmdc_io_lpm: + ldr r9, [r8], #0x8 + str r6, [r11, r9] + subs r7, r7, #0x1 + bne set_mmdc_io_lpm + + cmp r3, #MXC_CPU_IMX6SL + bne set_mmdc_io_lpm_done + ldr r6, =0x1000 + ldr r9, [r8], #0x8 + str r6, [r11, r9] + ldr r9, [r8], #0x8 + str r6, [r11, r9] + ldr r6, =0x80000 + ldr r9, [r8] + str r6, [r11, r9] +set_mmdc_io_lpm_done: + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r6, [r11, #MX6Q_GPC_IMR1] + ldr r7, [r11, #MX6Q_GPC_IMR2] + ldr r8, [r11, #MX6Q_GPC_IMR3] + ldr r9, [r11, #MX6Q_GPC_IMR4] + + ldr r10, =0xffffffff + str r10, [r11, #MX6Q_GPC_IMR1] + str r10, [r11, #MX6Q_GPC_IMR2] + str r10, [r11, #MX6Q_GPC_IMR3] + str r10, [r11, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 32 (1ms), Minimum RBC delay should be + * 400us for the analog LDOs to power down. + */ + ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r10, [r11, #MX6Q_CCM_CCR] + bic r10, r10, #(0x3f << 21) + orr r10, r10, #(0x20 << 21) + str r10, [r11, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r10, [r11, #MX6Q_CCM_CCR] + orr r10, r10, #(0x1 << 27) + str r10, [r11, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r6, [r11, #MX6Q_GPC_IMR1] + str r7, [r11, #MX6Q_GPC_IMR2] + str r8, [r11, #MX6Q_GPC_IMR3] + str r9, [r11, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 1GHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r6, =2000 +rbc_loop: + subs r6, r6, #0x1 + bne rbc_loop + + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + /* + * run to here means there is pending + * wakeup source, system should auto + * resume, we need to restore MMDC IO first + */ + mov r5, #0x0 + resume_mmdc + + /* return to suspend finish */ + mov pc, lr + +resume: + /* invalidate L1 I-cache first */ + mov r6, #0x0 + mcr p15, 0, r6, c7, c5, 0 + mcr p15, 0, r6, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r6, #0x1800 + mcr p15, 0, r6, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r11, #MX6Q_SRC_GPR1] + str r7, [r11, #MX6Q_SRC_GPR2] + + ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET] + mov r5, #0x1 + resume_mmdc + + mov pc, lr +ENDPROC(imx6_suspend) + +/* + * The following code must assume it is running from physical address + * where absolute virtual addresses to the data section have to be + * turned into relative ones. + */ + +#ifdef CONFIG_CACHE_L2X0 + .macro pl310_resume + adr r0, l2x0_saved_regs_offset + ldr r2, [r0] + add r2, r2, r0 + ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 + ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value + str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl + mov r1, #0x1 + str r1, [r0, #L2X0_CTRL] @ re-enable L2 + .endm + +l2x0_saved_regs_offset: + .word l2x0_saved_regs - . + +#else + .macro pl310_resume + .endm +#endif + +ENTRY(v7_cpu_resume) + bl v7_invalidate_l1 + pl310_resume + b cpu_resume +ENDPROC(v7_cpu_resume) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 1a3a5f615770..65222ea0df6d 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -25,6 +25,7 @@ #include <linux/irq.h> #include <linux/clockchips.h> #include <linux/clk.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/sched_clock.h> @@ -116,11 +117,22 @@ static u64 notrace mxc_read_sched_clock(void) return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; } +static struct delay_timer imx_delay_timer; + +static unsigned long imx_read_current_timer(void) +{ + return __raw_readl(sched_clock_reg); +} + static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); + imx_delay_timer.read_current_timer = &imx_read_current_timer; + imx_delay_timer.freq = c; + register_current_timer_delay(&imx_delay_timer); + sched_clock_reg = reg; sched_clock_register(mxc_read_sched_clock, 32, c); diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index fe8319ad3158..df4b26340ae4 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -106,13 +106,6 @@ config ARCH_KIRKWOOD_DT Say 'Y' here if you want your kernel to support the Marvell Kirkwood using flattened device tree. -config MACH_MV88F6281GTW_GE_DT - bool "Marvell 88F6281 GTW GE Board (Flattened Device Tree)" - depends on ARCH_KIRKWOOD_DT - help - Say 'Y' here if you want your kernel to support the - Marvell 88F6281 GTW GE Board (Flattened Device Tree). - endmenu endif diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 144b51102939..3a72c5c6e747 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -1,5 +1,4 @@ -obj-y += common.o pcie.o -obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o +obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o common.o pcie.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o @@ -13,4 +12,3 @@ obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o -obj-$(CONFIG_MACH_MV88F6281GTW_GE_DT) += board-mv88f6281gtw_ge.o diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 78188159484d..2801da49e2a3 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -19,11 +19,84 @@ #include <linux/of_platform.h> #include <linux/dma-mapping.h> #include <linux/irqchip.h> -#include <linux/kexec.h> +#include <asm/hardware/cache-feroceon-l2.h> #include <asm/mach/arch.h> +#include <asm/mach/map.h> #include <mach/bridge-regs.h> #include <plat/common.h> -#include "common.h" +#include <plat/pcie.h> +#include "pm.h" + +static struct map_desc kirkwood_io_desc[] __initdata = { + { + .virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), + .length = KIRKWOOD_REGS_SIZE, + .type = MT_DEVICE, + }, +}; + +static void __init kirkwood_map_io(void) +{ + iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); +} + +static struct resource kirkwood_cpufreq_resources[] = { + [0] = { + .start = CPU_CONTROL_PHYS, + .end = CPU_CONTROL_PHYS + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device kirkwood_cpufreq_device = { + .name = "kirkwood-cpufreq", + .id = -1, + .num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources), + .resource = kirkwood_cpufreq_resources, +}; + +static void __init kirkwood_cpufreq_init(void) +{ + platform_device_register(&kirkwood_cpufreq_device); +} + +static struct resource kirkwood_cpuidle_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = DDR_OPERATION_BASE, + .end = DDR_OPERATION_BASE + 3, + }, +}; + +static struct platform_device kirkwood_cpuidle = { + .name = "kirkwood_cpuidle", + .id = -1, + .resource = kirkwood_cpuidle_resource, + .num_resources = 1, +}; + +static void __init kirkwood_cpuidle_init(void) +{ + platform_device_register(&kirkwood_cpuidle); +} + +/* Temporary here since mach-mvebu has a function we can use */ +static void kirkwood_restart(enum reboot_mode mode, const char *cmd) +{ + /* + * Enable soft reset to assert RSTOUTn. + */ + writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); + + /* + * Assert soft reset. + */ + writel(SOFT_RESET, SYSTEM_SOFT_RESET); + + while (1) + ; +} #define MV643XX_ETH_MAC_ADDR_LOW 0x0414 #define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 @@ -104,35 +177,35 @@ eth_fixup_skip: } } -static void __init kirkwood_dt_init(void) +/* + * Disable propagation of mbus errors to the CPU local bus, as this + * causes mbus errors (which can occur for example for PCI aborts) to + * throw CPU aborts, which we're not set up to deal with. + */ +static void __init kirkwood_disable_mbus_error_propagation(void) { - pr_info("Kirkwood: %s.\n", kirkwood_id()); + void __iomem *cpu_config; - /* - * Disable propagation of mbus errors to the CPU local bus, - * as this causes mbus errors (which can occur for example - * for PCI aborts) to throw CPU aborts, which we're not set - * up to deal with. - */ - writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); + cpu_config = ioremap(CPU_CONFIG_PHYS, 4); + writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config); + iounmap(cpu_config); +} - BUG_ON(mvebu_mbus_dt_init()); +static void __init kirkwood_dt_init(void) +{ + kirkwood_disable_mbus_error_propagation(); - kirkwood_l2_init(); + BUG_ON(mvebu_mbus_dt_init()); +#ifdef CONFIG_CACHE_FEROCEON_L2 + feroceon_of_init(); +#endif kirkwood_cpufreq_init(); kirkwood_cpuidle_init(); kirkwood_pm_init(); kirkwood_dt_eth_fixup(); -#ifdef CONFIG_KEXEC - kexec_reinit = kirkwood_enable_pcie; -#endif - - if (of_machine_is_compatible("marvell,mv88f6281gtw-ge")) - mv88f6281gtw_ge_init(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c b/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c deleted file mode 100644 index ee5eea678c11..000000000000 --- a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c - * - * Marvell 88F6281 GTW GE Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/irq.h> -#include <linux/timer.h> -#include <linux/mv643xx_eth.h> -#include <linux/ethtool.h> -#include <linux/gpio.h> -#include <net/dsa.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/pci.h> -#include <mach/kirkwood.h> -#include "common.h" - -static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = { - .port_names[0] = "lan1", - .port_names[1] = "lan2", - .port_names[2] = "lan3", - .port_names[3] = "lan4", - .port_names[4] = "wan", - .port_names[5] = "cpu", -}; - -static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = { - .nr_chips = 1, - .chip = &mv88f6281gtw_ge_switch_chip_data, -}; - -void __init mv88f6281gtw_ge_init(void) -{ - kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data); - kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ); -} diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index f3407a5db216..255f33a3903c 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -25,10 +25,10 @@ #include <asm/page.h> #include <asm/mach/map.h> #include <asm/mach/time.h> +#include <asm/hardware/cache-feroceon-l2.h> #include <mach/kirkwood.h> #include <mach/bridge-regs.h> #include <linux/platform_data/asoc-kirkwood.h> -#include <plat/cache-feroceon-l2.h> #include <linux/platform_data/mmc-mvsdio.h> #include <linux/platform_data/mtd-orion_nand.h> #include <linux/platform_data/usb-ehci-orion.h> @@ -36,6 +36,7 @@ #include <plat/time.h> #include <linux/platform_data/dma-mv_xor.h> #include "common.h" +#include "pm.h" /* These can go away once Kirkwood uses the mvebu-mbus DT binding */ #define KIRKWOOD_MBUS_NAND_TARGET 0x01 diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index 05fd648df543..832a4e2ab8d7 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h @@ -58,19 +58,6 @@ void kirkwood_cpufreq_init(void); void kirkwood_restart(enum reboot_mode, const char *); void kirkwood_clk_init(void); -#ifdef CONFIG_PM -void kirkwood_pm_init(void); -#else -static inline void kirkwood_pm_init(void) {}; -#endif - -/* board init functions for boards not fully converted to fdt */ -#ifdef CONFIG_MACH_MV88F6281GTW_GE_DT -void mv88f6281gtw_ge_init(void); -#else -static inline void mv88f6281gtw_ge_init(void) {}; -#endif - /* early init functions not converted to fdt yet */ char *kirkwood_id(void); void kirkwood_l2_init(void); diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index 8b9d1c9ff199..6e5077e2ec26 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -14,6 +14,7 @@ #include <mach/kirkwood.h> #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100) +#define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100) #define CPU_CONFIG_ERROR_PROP 0x00000004 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) @@ -79,5 +80,6 @@ #define CGC_RESERVED (0x6 << 21) #define MEMORY_PM_CTRL (BRIDGE_VIRT_BASE + 0x118) +#define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x118) #endif diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c index c6ab8d9303a5..8e5e0329d04c 100644 --- a/arch/arm/mach-kirkwood/pm.c +++ b/arch/arm/mach-kirkwood/pm.c @@ -21,15 +21,16 @@ #include "common.h" static void __iomem *ddr_operation_base; +static void __iomem *memory_pm_ctrl; static void kirkwood_low_power(void) { u32 mem_pm_ctrl; - mem_pm_ctrl = readl(MEMORY_PM_CTRL); + mem_pm_ctrl = readl(memory_pm_ctrl); /* Set peripherals to low-power mode */ - writel_relaxed(~0, MEMORY_PM_CTRL); + writel_relaxed(~0, memory_pm_ctrl); /* Set DDR in self-refresh */ writel_relaxed(0x7, ddr_operation_base); @@ -41,7 +42,7 @@ static void kirkwood_low_power(void) */ cpu_do_idle(); - writel_relaxed(mem_pm_ctrl, MEMORY_PM_CTRL); + writel_relaxed(mem_pm_ctrl, memory_pm_ctrl); } static int kirkwood_suspend_enter(suspend_state_t state) @@ -69,5 +70,7 @@ static const struct platform_suspend_ops kirkwood_suspend_ops = { void __init kirkwood_pm_init(void) { ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4); + memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4); + suspend_set_ops(&kirkwood_suspend_ops); } diff --git a/arch/arm/mach-kirkwood/pm.h b/arch/arm/mach-kirkwood/pm.h new file mode 100644 index 000000000000..21e7530f368b --- /dev/null +++ b/arch/arm/mach-kirkwood/pm.h @@ -0,0 +1,26 @@ +/* + * Power Management driver for Marvell Kirkwood SoCs + * + * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com> + * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, + * version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_KIRKWOOD_PM_H +#define __ARCH_KIRKWOOD_PM_H + +#ifdef CONFIG_PM +void kirkwood_pm_init(void); +#else +static inline void kirkwood_pm_init(void) {}; +#endif + +#endif diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h index 0a4899b7d85c..572479a3c7be 100644 --- a/arch/arm/mach-msm/common.h +++ b/arch/arm/mach-msm/common.h @@ -23,8 +23,6 @@ extern void msm_map_qsd8x50_io(void); extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, unsigned int mtype, void *caller); -extern struct smp_operations msm_smp_ops; - struct msm_mmc_platform_data; extern void msm_add_devices(void); diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 75062eff2494..e6ac679bece9 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -15,11 +15,11 @@ #include <linux/ata_platform.h> #include <linux/clk-provider.h> #include <linux/ethtool.h> +#include <asm/hardware/cache-feroceon-l2.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <mach/mv78xx0.h> #include <mach/bridge-regs.h> -#include <plat/cache-feroceon-l2.h> #include <linux/platform_data/usb-ehci-orion.h> #include <linux/platform_data/mtd-orion_nand.h> #include <plat/time.h> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index ca004aceaf8e..3f73eecbcfb0 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -1,5 +1,5 @@ config ARCH_MVEBU - bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7 + bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V5) select ARCH_SUPPORTS_BIG_ENDIAN select CLKSRC_MMIO select GENERIC_IRQ_CHIP @@ -15,32 +15,95 @@ config ARCH_MVEBU if ARCH_MVEBU -menu "Marvell SOC with device tree" +menu "Marvell EBU SoC variants" -config MACH_ARMADA_370_XP +config MACH_MVEBU_V7 bool select ARMADA_370_XP_TIMER select CACHE_L2X0 - select CPU_PJ4B config MACH_ARMADA_370 - bool "Marvell Armada 370 boards" + bool "Marvell Armada 370 boards" if ARCH_MULTI_V7 select ARMADA_370_CLK - select MACH_ARMADA_370_XP + select CPU_PJ4B + select MACH_MVEBU_V7 select PINCTRL_ARMADA_370 help Say 'Y' here if you want your kernel to support boards based on the Marvell Armada 370 SoC with device tree. +config MACH_ARMADA_375 + bool "Marvell Armada 375 boards" if ARCH_MULTI_V7 + select ARM_ERRATA_720789 + select ARM_ERRATA_753970 + select ARM_GIC + select ARMADA_375_CLK + select CPU_V7 + select MACH_MVEBU_V7 + select PINCTRL_ARMADA_375 + help + Say 'Y' here if you want your kernel to support boards based + on the Marvell Armada 375 SoC with device tree. + +config MACH_ARMADA_38X + bool "Marvell Armada 380/385 boards" if ARCH_MULTI_V7 + select ARM_ERRATA_720789 + select ARM_ERRATA_753970 + select ARM_GIC + select ARMADA_38X_CLK + select CPU_V7 + select MACH_MVEBU_V7 + select PINCTRL_ARMADA_38X + help + Say 'Y' here if you want your kernel to support boards based + on the Marvell Armada 380/385 SoC with device tree. + config MACH_ARMADA_XP - bool "Marvell Armada XP boards" + bool "Marvell Armada XP boards" if ARCH_MULTI_V7 select ARMADA_XP_CLK - select MACH_ARMADA_370_XP + select CPU_PJ4B + select MACH_MVEBU_V7 select PINCTRL_ARMADA_XP help Say 'Y' here if you want your kernel to support boards based on the Marvell Armada XP SoC with device tree. +config MACH_DOVE + bool "Marvell Dove boards" if ARCH_MULTI_V7 + select CACHE_L2X0 + select CPU_PJ4 + select DOVE_CLK + select ORION_IRQCHIP + select ORION_TIMER + select PINCTRL_DOVE + help + Say 'Y' here if you want your kernel to support the + Marvell Dove using flattened device tree. + +config MACH_KIRKWOOD + bool "Marvell Kirkwood boards" if ARCH_MULTI_V5 + select ARCH_HAS_CPUFREQ + select ARCH_REQUIRE_GPIOLIB + select CPU_FEROCEON + select KIRKWOOD_CLK + select OF_IRQ + select ORION_IRQCHIP + select ORION_TIMER + select PCI + select PCI_QUIRKS + select PINCTRL_KIRKWOOD + select USE_OF + help + Say 'Y' here if you want your kernel to support boards based + on the Marvell Kirkwood device tree. + +config MACH_T5325 + bool "HP T5325 thin client" + depends on MACH_KIRKWOOD + help + Say 'Y' here if you want your kernel to support the + HP T5325 Thin client + endmenu endif diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index d99846103bbb..a63e43b6b451 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -3,7 +3,11 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a -obj-y += coherency.o coherency_ll.o pmsu.o system-controller.o mvebu-soc-id.o -obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o +obj-y += system-controller.o mvebu-soc-id.o +obj-$(CONFIG_MACH_MVEBU_V7) += board-v7.o +obj-$(CONFIG_MACH_DOVE) += dove.o +obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +obj-$(CONFIG_MACH_KIRKWOOD) += kirkwood.o kirkwood-pm.o +obj-$(CONFIG_MACH_T5325) += board-t5325.o diff --git a/arch/arm/mach-mvebu/board-t5325.c b/arch/arm/mach-mvebu/board-t5325.c new file mode 100644 index 000000000000..65ace6db9f28 --- /dev/null +++ b/arch/arm/mach-mvebu/board-t5325.c @@ -0,0 +1,41 @@ +/* + * HP T5325 Board Setup + * + * Copyright (C) 2014 + * + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <sound/alc5623.h> +#include "board.h" + +static struct platform_device hp_t5325_audio_device = { + .name = "t5325-audio", + .id = -1, +}; + +static struct alc5623_platform_data alc5621_data = { + .add_ctrl = 0x3700, + .jack_det_ctrl = 0x4810, +}; + +static struct i2c_board_info i2c_board_info[] __initdata = { + { + I2C_BOARD_INFO("alc5621", 0x1a), + .platform_data = &alc5621_data, + }, +}; + +void __init t5325_init(void) +{ + i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info)); + platform_device_register(&hp_t5325_audio_device); +} diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/board-v7.c index a57cb36d52af..333fca8fdc41 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -32,7 +32,28 @@ #include "coherency.h" #include "mvebu-soc-id.h" -static void __init armada_370_xp_timer_and_clk_init(void) +/* + * Early versions of Armada 375 SoC have a bug where the BootROM + * leaves an external data abort pending. The kernel is hit by this + * data abort as soon as it enters userspace, because it unmasks the + * data aborts at this moment. We register a custom abort handler + * below to ignore the first data abort to work around this + * problem. + */ +static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + static int ignore_first; + + if (!ignore_first && fsr == 0x1406) { + ignore_first = 1; + return 0; + } + + return 1; +} + +static void __init mvebu_timer_and_clk_init(void) { of_clk_init(NULL); clocksource_of_init(); @@ -41,6 +62,10 @@ static void __init armada_370_xp_timer_and_clk_init(void) #ifdef CONFIG_CACHE_L2X0 l2x0_of_init(0, ~0UL); #endif + + if (of_machine_is_compatible("marvell,armada375")) + hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0, + "imprecise external abort"); } static void __init i2c_quirk(void) @@ -71,7 +96,7 @@ static void __init i2c_quirk(void) return; } -static void __init armada_370_xp_dt_init(void) +static void __init mvebu_dt_init(void) { if (of_machine_is_compatible("plathome,openblocks-ax3-4")) i2c_quirk(); @@ -83,10 +108,33 @@ static const char * const armada_370_xp_dt_compat[] = { NULL, }; -DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") +DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)") .smp = smp_ops(armada_xp_smp_ops), - .init_machine = armada_370_xp_dt_init, - .init_time = armada_370_xp_timer_and_clk_init, + .init_machine = mvebu_dt_init, + .init_time = mvebu_timer_and_clk_init, .restart = mvebu_restart, .dt_compat = armada_370_xp_dt_compat, MACHINE_END + +static const char * const armada_375_dt_compat[] = { + "marvell,armada375", + NULL, +}; + +DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)") + .init_time = mvebu_timer_and_clk_init, + .restart = mvebu_restart, + .dt_compat = armada_375_dt_compat, +MACHINE_END + +static const char * const armada_38x_dt_compat[] = { + "marvell,armada380", + "marvell,armada385", + NULL, +}; + +DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)") + .init_time = mvebu_timer_and_clk_init, + .restart = mvebu_restart, + .dt_compat = armada_38x_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-mvebu/board.h b/arch/arm/mach-mvebu/board.h new file mode 100644 index 000000000000..de7f0a191394 --- /dev/null +++ b/arch/arm/mach-mvebu/board.h @@ -0,0 +1,22 @@ +/* + * Board functions for Marvell System On Chip + * + * Copyright (C) 2014 + * + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_MVEBU_BOARD_H +#define __ARCH_MVEBU_BOARD_H + +#ifdef CONFIG_MACH_T5325 +void t5325_init(void); +#else +static inline void t5325_init(void) {}; +#endif + +#endif diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-mvebu/dove.c index 49fa9abd09da..5e5a43624237 100644 --- a/arch/arm/mach-dove/board-dt.c +++ b/arch/arm/mach-mvebu/dove.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-dove/board-dt.c + * arch/arm/mach-mvebu/dove.c * * Marvell Dove 88AP510 System On Chip FDT Board * @@ -9,17 +9,14 @@ */ #include <linux/init.h> -#include <linux/clk-provider.h> +#include <linux/mbus.h> #include <linux/of.h> #include <linux/of_platform.h> #include <asm/hardware/cache-tauros2.h> #include <asm/mach/arch.h> -#include <mach/dove.h> -#include <mach/pm.h> -#include <plat/common.h> #include "common.h" -static void __init dove_dt_init(void) +static void __init dove_init(void) { pr_info("Dove 88AP510 SoC\n"); @@ -30,14 +27,13 @@ static void __init dove_dt_init(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -static const char * const dove_dt_board_compat[] = { +static const char * const dove_dt_compat[] = { "marvell,dove", NULL }; -DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") - .map_io = dove_map_io, - .init_machine = dove_dt_init, - .restart = dove_restart, - .dt_compat = dove_dt_board_compat, +DT_MACHINE_START(DOVE_DT, "Marvell Dove") + .init_machine = dove_init, + .restart = mvebu_restart, + .dt_compat = dove_dt_compat, MACHINE_END diff --git a/arch/arm/mach-mvebu/kirkwood-pm.c b/arch/arm/mach-mvebu/kirkwood-pm.c new file mode 100644 index 000000000000..cbb816f2120c --- /dev/null +++ b/arch/arm/mach-mvebu/kirkwood-pm.c @@ -0,0 +1,76 @@ +/* + * Power Management driver for Marvell Kirkwood SoCs + * + * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com> + * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, + * version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/suspend.h> +#include <linux/io.h> +#include "kirkwood.h" + +static void __iomem *ddr_operation_base; +static void __iomem *memory_pm_ctrl; + +static void kirkwood_low_power(void) +{ + u32 mem_pm_ctrl; + + mem_pm_ctrl = readl(memory_pm_ctrl); + + /* Set peripherals to low-power mode */ + writel_relaxed(~0, memory_pm_ctrl); + + /* Set DDR in self-refresh */ + writel_relaxed(0x7, ddr_operation_base); + + /* + * Set CPU in wait-for-interrupt state. + * This disables the CPU core clocks, + * the array clocks, and also the L2 controller. + */ + cpu_do_idle(); + + writel_relaxed(mem_pm_ctrl, memory_pm_ctrl); +} + +static int kirkwood_suspend_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + kirkwood_low_power(); + break; + default: + return -EINVAL; + } + return 0; +} + +static int kirkwood_pm_valid_standby(suspend_state_t state) +{ + return state == PM_SUSPEND_STANDBY; +} + +static const struct platform_suspend_ops kirkwood_suspend_ops = { + .enter = kirkwood_suspend_enter, + .valid = kirkwood_pm_valid_standby, +}; + +int __init kirkwood_pm_init(void) +{ + ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4); + memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4); + + suspend_set_ops(&kirkwood_suspend_ops); + return 0; +} diff --git a/arch/arm/mach-mvebu/kirkwood-pm.h b/arch/arm/mach-mvebu/kirkwood-pm.h new file mode 100644 index 000000000000..21e7530f368b --- /dev/null +++ b/arch/arm/mach-mvebu/kirkwood-pm.h @@ -0,0 +1,26 @@ +/* + * Power Management driver for Marvell Kirkwood SoCs + * + * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com> + * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, + * version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_KIRKWOOD_PM_H +#define __ARCH_KIRKWOOD_PM_H + +#ifdef CONFIG_PM +void kirkwood_pm_init(void); +#else +static inline void kirkwood_pm_init(void) {}; +#endif + +#endif diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c new file mode 100644 index 000000000000..120207fc36f1 --- /dev/null +++ b/arch/arm/mach-mvebu/kirkwood.c @@ -0,0 +1,199 @@ +/* + * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net> + * + * arch/arm/mach-mvebu/kirkwood.c + * + * Flattened Device Tree board initialization + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_net.h> +#include <linux/of_platform.h> +#include <linux/slab.h> +#include <asm/hardware/cache-feroceon-l2.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include "kirkwood.h" +#include "kirkwood-pm.h" +#include "common.h" +#include "board.h" + +static struct resource kirkwood_cpufreq_resources[] = { + [0] = { + .start = CPU_CONTROL_PHYS, + .end = CPU_CONTROL_PHYS + 3, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device kirkwood_cpufreq_device = { + .name = "kirkwood-cpufreq", + .id = -1, + .num_resources = ARRAY_SIZE(kirkwood_cpufreq_resources), + .resource = kirkwood_cpufreq_resources, +}; + +static void __init kirkwood_cpufreq_init(void) +{ + platform_device_register(&kirkwood_cpufreq_device); +} + +static struct resource kirkwood_cpuidle_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = DDR_OPERATION_BASE, + .end = DDR_OPERATION_BASE + 3, + }, +}; + +static struct platform_device kirkwood_cpuidle = { + .name = "kirkwood_cpuidle", + .id = -1, + .resource = kirkwood_cpuidle_resource, + .num_resources = 1, +}; + +static void __init kirkwood_cpuidle_init(void) +{ + platform_device_register(&kirkwood_cpuidle); +} + +#define MV643XX_ETH_MAC_ADDR_LOW 0x0414 +#define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 + +static void __init kirkwood_dt_eth_fixup(void) +{ + struct device_node *np; + + /* + * The ethernet interfaces forget the MAC address assigned by u-boot + * if the clocks are turned off. Usually, u-boot on kirkwood boards + * has no DT support to properly set local-mac-address property. + * As a workaround, we get the MAC address from mv643xx_eth registers + * and update the port device node if no valid MAC address is set. + */ + for_each_compatible_node(np, NULL, "marvell,kirkwood-eth-port") { + struct device_node *pnp = of_get_parent(np); + struct clk *clk; + struct property *pmac; + void __iomem *io; + u8 *macaddr; + u32 reg; + + if (!pnp) + continue; + + /* skip disabled nodes or nodes with valid MAC address*/ + if (!of_device_is_available(pnp) || of_get_mac_address(np)) + goto eth_fixup_skip; + + clk = of_clk_get(pnp, 0); + if (IS_ERR(clk)) + goto eth_fixup_skip; + + io = of_iomap(pnp, 0); + if (!io) + goto eth_fixup_no_map; + + /* ensure port clock is not gated to not hang CPU */ + clk_prepare_enable(clk); + + /* store MAC address register contents in local-mac-address */ + pr_err(FW_INFO "%s: local-mac-address is not set\n", + np->full_name); + + pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL); + if (!pmac) + goto eth_fixup_no_mem; + + pmac->value = pmac + 1; + pmac->length = 6; + pmac->name = kstrdup("local-mac-address", GFP_KERNEL); + if (!pmac->name) { + kfree(pmac); + goto eth_fixup_no_mem; + } + + macaddr = pmac->value; + reg = readl(io + MV643XX_ETH_MAC_ADDR_HIGH); + macaddr[0] = (reg >> 24) & 0xff; + macaddr[1] = (reg >> 16) & 0xff; + macaddr[2] = (reg >> 8) & 0xff; + macaddr[3] = reg & 0xff; + + reg = readl(io + MV643XX_ETH_MAC_ADDR_LOW); + macaddr[4] = (reg >> 8) & 0xff; + macaddr[5] = reg & 0xff; + + of_update_property(np, pmac); + +eth_fixup_no_mem: + iounmap(io); + clk_disable_unprepare(clk); +eth_fixup_no_map: + clk_put(clk); +eth_fixup_skip: + of_node_put(pnp); + } +} + +/* + * Disable propagation of mbus errors to the CPU local bus, as this + * causes mbus errors (which can occur for example for PCI aborts) to + * throw CPU aborts, which we're not set up to deal with. + */ +void kirkwood_disable_mbus_error_propagation(void) +{ + void __iomem *cpu_config; + + cpu_config = ioremap(CPU_CONFIG_PHYS, 4); + writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config); +} + +static struct of_dev_auxdata auxdata[] __initdata = { + OF_DEV_AUXDATA("marvell,kirkwood-audio", 0xf10a0000, + "mvebu-audio", NULL), + { /* sentinel */ } +}; + +static void __init kirkwood_dt_init(void) +{ + kirkwood_disable_mbus_error_propagation(); + + BUG_ON(mvebu_mbus_dt_init()); + +#ifdef CONFIG_CACHE_FEROCEON_L2 + feroceon_of_init(); +#endif + kirkwood_cpufreq_init(); + kirkwood_cpuidle_init(); + + kirkwood_pm_init(); + kirkwood_dt_eth_fixup(); + + if (of_machine_is_compatible("hp,t5325")) + t5325_init(); + + of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL); +} + +static const char * const kirkwood_dt_board_compat[] = { + "marvell,kirkwood", + NULL +}; + +DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)") + /* Maintainer: Jason Cooper <jason@lakedaemon.net> */ + .init_machine = kirkwood_dt_init, + .restart = mvebu_restart, + .dt_compat = kirkwood_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-mvebu/kirkwood.h b/arch/arm/mach-mvebu/kirkwood.h new file mode 100644 index 000000000000..89f3d1f51643 --- /dev/null +++ b/arch/arm/mach-mvebu/kirkwood.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-mvebu/kirkwood.h + * + * Generic definitions for Marvell Kirkwood SoC flavors: + * 88F6180, 88F6192 and 88F6281. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 +#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000) +#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) + +#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418) + +#define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100) +#define CPU_CONFIG_ERROR_PROP 0x00000004 + +#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104) +#define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118) diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c index f3b325f6cbd4..f3d4cf53f746 100644 --- a/arch/arm/mach-mvebu/mvebu-soc-id.c +++ b/arch/arm/mach-mvebu/mvebu-soc-id.c @@ -38,6 +38,7 @@ static bool is_id_valid; static const struct of_device_id mvebu_pcie_of_match_table[] = { { .compatible = "marvell,armada-xp-pcie", }, { .compatible = "marvell,armada-370-pcie", }, + { .compatible = "marvell,kirkwood-pcie" }, {}, }; diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index e6e300afe836..614ba6832ff3 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -1,5 +1,5 @@ /* - * System controller support for Armada 370 and XP platforms. + * System controller support for Armada 370, 375 and XP platforms. * * Copyright (C) 2012 Marvell * @@ -11,7 +11,7 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. * - * The Armada 370 and Armada XP SoCs both have a range of + * The Armada 370, 375 and Armada XP SoCs have a range of * miscellaneous registers, that do not belong to a particular device, * but rather provide system-level features. This basic * system-controller driver provides a device tree binding for those @@ -47,6 +47,13 @@ static const struct mvebu_system_controller armada_370_xp_system_controller = { .system_soft_reset = 0x1, }; +static const struct mvebu_system_controller armada_375_system_controller = { + .rstoutn_mask_offset = 0x54, + .system_soft_reset_offset = 0x58, + .rstoutn_mask_reset_out_en = 0x1, + .system_soft_reset = 0x1, +}; + static const struct mvebu_system_controller orion_system_controller = { .rstoutn_mask_offset = 0x108, .system_soft_reset_offset = 0x10c, @@ -61,6 +68,9 @@ static const struct of_device_id of_system_controller_table[] = { }, { .compatible = "marvell,armada-370-xp-system-controller", .data = (void *) &armada_370_xp_system_controller, + }, { + .compatible = "marvell,armada-375-system-controller", + .data = (void *) &armada_375_system_controller, }, { /* end of list */ }, }; diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 27fc52d418a5..5c22c0899e9c 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -149,12 +149,6 @@ config SOC_TI81XX depends on ARCH_OMAP3 default y -config OMAP_PACKAGE_ZAF - bool - -config OMAP_PACKAGE_ZAC - bool - config OMAP_PACKAGE_CBC bool @@ -264,7 +258,6 @@ config MACH_NOKIA_N8X0 default y select MACH_NOKIA_N810 select MACH_NOKIA_N810_WIMAX - select OMAP_PACKAGE_ZAC config MACH_NOKIA_RX51 bool "Nokia N900 (RX-51) phone" diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index e6eec6f72fd3..8421f38cf445 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -60,6 +60,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o +obj-$(CONFIG_SOC_AM43XX) += omap4-restart.o obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 8e3daa11602b..bc6013fbb773 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -229,8 +229,9 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") .init_late = am43xx_init_late, .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, - .init_time = omap3_sync32k_timer_init, + .init_time = omap3_gptimer_timer_init, .dt_compat = am43_boards_compat, + .restart = omap44xx_restart, MACHINE_END #endif diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 47f9562ca7aa..2649ce445845 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -306,7 +306,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, ref_rate = __clk_get_rate(dd->clk_ref); clk_name = __clk_get_name(hw->clk); - pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", + pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n", clk_name, target_rate); scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR); @@ -342,7 +342,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, if (r == DPLL_MULT_UNDERFLOW) continue; - pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", + pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n", clk_name, m, n, new_rate); if (target_rate == new_rate) { @@ -354,7 +354,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, } if (target_rate != new_rate) { - pr_debug("clock: %s: cannot round to rate %ld\n", + pr_debug("clock: %s: cannot round to rate %lu\n", clk_name, target_rate); return ~0; } diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index 731ca134348c..f5c4731b6f06 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -254,6 +254,11 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs) * */ +void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs) +{ + _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); +} + /** * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state * @part: PRCM partition ID that the CM_CLKCTRL register exists in @@ -404,8 +409,17 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm) static int omap4_clkdm_sleep(struct clockdomain *clkdm) { - omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, - clkdm->cm_inst, clkdm->clkdm_offs); + if (clkdm->flags & CLKDM_CAN_HWSUP) + omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs); + else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) + omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs); + else + return -EINVAL; + return 0; } diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 3c418ea54bbe..fcd8036af910 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -525,7 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, * stuff is inherited for free */ - if (!ret) + if (!ret && clk_get_parent(hw->clk) != new_parent) __clk_reparent(hw->clk, new_parent); return 0; diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 9428c5f9d4f2..157412e4273a 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -465,8 +465,18 @@ void __init omap3xxx_check_revision(void) } break; case 0xb98c: - omap_revision = AM437X_REV_ES1_0; - cpu_rev = "1.0"; + switch (rev) { + case 0: + omap_revision = AM437X_REV_ES1_0; + cpu_rev = "1.0"; + break; + case 1: + /* FALLTHROUGH */ + default: + omap_revision = AM437X_REV_ES1_1; + cpu_rev = "1.1"; + break; + } break; case 0xb8f2: switch (rev) { @@ -657,6 +667,8 @@ static const char * __init omap_get_family(void) return kasprintf(GFP_KERNEL, "OMAP4"); else if (soc_is_omap54xx()) return kasprintf(GFP_KERNEL, "OMAP5"); + else if (soc_is_am43xx()) + return kasprintf(GFP_KERNEL, "AM43xx"); else return kasprintf(GFP_KERNEL, "Unknown"); } diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index af432b191255..f14f9ac2dca1 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -604,6 +604,7 @@ void __init am43xx_init_early(void) omap_prm_base_init(); omap_cm_base_init(); omap3xxx_check_revision(); + am33xx_check_features(); am43xx_powerdomains_init(); am43xx_clockdomains_init(); am43xx_hwmod_init(); diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index a722330d4d53..d121fb6df4e6 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -63,9 +63,6 @@ #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ #define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ #define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */ -#define OMAP_PACKAGE_ZAC 2 /* 24xx 447-pin POP */ -#define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */ - #define OMAP_MUX_NR_MODES 8 /* Available modes */ #define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 9002fca76699..5c2cc8083fdd 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -719,6 +719,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_ls__uart4, &am33xx_l4_ls__uart5, &am33xx_l4_ls__uart6, + &am33xx_l4_ls__spinlock, &am33xx_l4_ls__elm, &am33xx_l4_ls__epwmss0, &am33xx_epwmss0__ecap0, diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c index 280f3c58abe5..05fcf6de44ee 100644 --- a/arch/arm/mach-omap2/prminst44xx.c +++ b/arch/arm/mach-omap2/prminst44xx.c @@ -25,6 +25,7 @@ #include "prminst44xx.h" #include "prm-regbits-44xx.h" #include "prcm44xx.h" +#include "prcm43xx.h" #include "prcm_mpu44xx.h" #include "soc.h" @@ -176,6 +177,8 @@ void omap4_prminst_global_warm_sw_reset(void) dev_inst = OMAP54XX_PRM_DEVICE_INST; else if (soc_is_dra7xx()) dev_inst = DRA7XX_PRM_DEVICE_INST; + else if (soc_is_am43xx()) + dev_inst = AM43XX_PRM_DEVICE_INST; else return; diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 076bd90a6ce0..30abcc8b20e0 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -438,7 +438,8 @@ IS_OMAP_TYPE(3430, 0x3430) #define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 << 8)) #define AM437X_CLASS 0x43700000 -#define AM437X_REV_ES1_0 AM437X_CLASS +#define AM437X_REV_ES1_0 (AM437X_CLASS | (0x10 << 8)) +#define AM437X_REV_ES1_1 (AM437X_CLASS | (0x11 << 8)) #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 74044aaf438b..b62de9f9d05c 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -604,7 +604,8 @@ OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", 2, "timer_sys_ck", NULL); #endif /* CONFIG_ARCH_OMAP3 */ -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \ + defined(CONFIG_SOC_AM43XX) OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, 1, "timer_sys_ck", "ti,timer-alwon"); #endif diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c index 830f69c3a3ce..bae617ef0b31 100644 --- a/arch/arm/mach-qcom/board.c +++ b/arch/arm/mach-qcom/board.c @@ -11,30 +11,16 @@ */ #include <linux/init.h> -#include <linux/of.h> -#include <linux/of_platform.h> #include <asm/mach/arch.h> -#include <asm/mach/map.h> - -extern struct smp_operations qcom_smp_ops; static const char * const qcom_dt_match[] __initconst = { "qcom,msm8660-surf", "qcom,msm8960-cdp", - NULL -}; - -static const char * const apq8074_dt_match[] __initconst = { "qcom,apq8074-dragonboard", NULL }; DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)") - .smp = smp_ops(qcom_smp_ops), .dt_compat = qcom_dt_match, MACHINE_END - -DT_MACHINE_START(APQ_DT, "Qualcomm (Flattened Device Tree)") - .dt_compat = apq8074_dt_match, -MACHINE_END diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c index 9c53ea70550d..d6908569ecaf 100644 --- a/arch/arm/mach-qcom/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c @@ -13,17 +13,36 @@ #include <linux/errno.h> #include <linux/delay.h> #include <linux/device.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <linux/smp.h> #include <linux/io.h> -#include <asm/cputype.h> #include <asm/smp_plat.h> #include "scm-boot.h" -#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 -#define SCSS_CPU1CORE_RESET 0xD80 -#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 +#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0 +#define SCSS_CPU1CORE_RESET 0x2d80 +#define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64 + +#define APCS_CPU_PWR_CTL 0x04 +#define PLL_CLAMP BIT(8) +#define CORE_PWRD_UP BIT(7) +#define COREPOR_RST BIT(5) +#define CORE_RST BIT(4) +#define L2DT_SLP BIT(3) +#define CLAMP BIT(0) + +#define APC_PWR_GATE_CTL 0x14 +#define BHS_CNT_SHIFT 24 +#define LDO_PWR_DWN_SHIFT 16 +#define LDO_BYP_SHIFT 8 +#define BHS_SEG_SHIFT 1 +#define BHS_EN BIT(0) + +#define APCS_SAW2_VCTL 0x14 +#define APCS_SAW2_2_VCTL 0x1c extern void secondary_startup(void); @@ -36,12 +55,6 @@ static void __ref qcom_cpu_die(unsigned int cpu) } #endif -static inline int get_core_count(void) -{ - /* 1 + the PART[1:0] field of MIDR */ - return ((read_cpuid_id() >> 4) & 3) + 1; -} - static void qcom_secondary_init(unsigned int cpu) { /* @@ -51,33 +64,220 @@ static void qcom_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -static void prepare_cold_cpu(unsigned int cpu) +static int scss_release_secondary(unsigned int cpu) +{ + struct device_node *node; + void __iomem *base; + + node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660"); + if (!node) { + pr_err("%s: can't find node\n", __func__); + return -ENXIO; + } + + base = of_iomap(node, 0); + of_node_put(node); + if (!base) + return -ENOMEM; + + writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); + writel_relaxed(0, base + SCSS_CPU1CORE_RESET); + writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); + mb(); + iounmap(base); + + return 0; +} + +static int kpssv1_release_secondary(unsigned int cpu) { + int ret = 0; + void __iomem *reg, *saw_reg; + struct device_node *cpu_node, *acc_node, *saw_node; + u32 val; + + cpu_node = of_get_cpu_node(cpu, NULL); + if (!cpu_node) + return -ENODEV; + + acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); + if (!acc_node) { + ret = -ENODEV; + goto out_acc; + } + + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + if (!saw_node) { + ret = -ENODEV; + goto out_saw; + } + + reg = of_iomap(acc_node, 0); + if (!reg) { + ret = -ENOMEM; + goto out_acc_map; + } + + saw_reg = of_iomap(saw_node, 0); + if (!saw_reg) { + ret = -ENOMEM; + goto out_saw_map; + } + + /* Turn on CPU rail */ + writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); + mb(); + udelay(512); + + /* Krait bring-up sequence */ + val = PLL_CLAMP | L2DT_SLP | CLAMP; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + val &= ~L2DT_SLP; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + ndelay(300); + + val |= COREPOR_RST; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(2); + + val &= ~CLAMP; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(2); + + val &= ~COREPOR_RST; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(100); + + val |= CORE_PWRD_UP; + writel_relaxed(val, reg + APCS_CPU_PWR_CTL); + mb(); + + iounmap(saw_reg); +out_saw_map: + iounmap(reg); +out_acc_map: + of_node_put(saw_node); +out_saw: + of_node_put(acc_node); +out_acc: + of_node_put(cpu_node); + return ret; +} + +static int kpssv2_release_secondary(unsigned int cpu) +{ + void __iomem *reg; + struct device_node *cpu_node, *l2_node, *acc_node, *saw_node; + void __iomem *l2_saw_base; + unsigned reg_val; int ret; - ret = scm_set_boot_addr(virt_to_phys(secondary_startup), - SCM_FLAG_COLDBOOT_CPU1); - if (ret == 0) { - void __iomem *sc1_base_ptr; - sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); - if (sc1_base_ptr) { - writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); - writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET); - writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP); - iounmap(sc1_base_ptr); - } - } else - printk(KERN_DEBUG "Failed to set secondary core boot " - "address\n"); + + cpu_node = of_get_cpu_node(cpu, NULL); + if (!cpu_node) + return -ENODEV; + + acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0); + if (!acc_node) { + ret = -ENODEV; + goto out_acc; + } + + l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0); + if (!l2_node) { + ret = -ENODEV; + goto out_l2; + } + + saw_node = of_parse_phandle(l2_node, "qcom,saw", 0); + if (!saw_node) { + ret = -ENODEV; + goto out_saw; + } + + reg = of_iomap(acc_node, 0); + if (!reg) { + ret = -ENOMEM; + goto out_map; + } + + l2_saw_base = of_iomap(saw_node, 0); + if (!l2_saw_base) { + ret = -ENOMEM; + goto out_saw_map; + } + + /* Turn on the BHS, turn off LDO Bypass and power down LDO */ + reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN; + writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); + mb(); + /* wait for the BHS to settle */ + udelay(1); + + /* Turn on BHS segments */ + reg_val |= 0x3f << BHS_SEG_SHIFT; + writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); + mb(); + /* wait for the BHS to settle */ + udelay(1); + + /* Finally turn on the bypass so that BHS supplies power */ + reg_val |= 0x3f << LDO_BYP_SHIFT; + writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); + + /* enable max phases */ + writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL); + mb(); + udelay(50); + + reg_val = COREPOR_RST | CLAMP; + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(2); + + reg_val &= ~CLAMP; + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); + mb(); + udelay(2); + + reg_val &= ~COREPOR_RST; + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); + mb(); + + reg_val |= CORE_PWRD_UP; + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); + mb(); + + ret = 0; + + iounmap(l2_saw_base); +out_saw_map: + iounmap(reg); +out_map: + of_node_put(saw_node); +out_saw: + of_node_put(l2_node); +out_l2: + of_node_put(acc_node); +out_acc: + of_node_put(cpu_node); + + return ret; } -static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle) +static DEFINE_PER_CPU(int, cold_boot_done); + +static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int)) { - static int cold_boot_done; + int ret = 0; - /* Only need to bring cpu out of reset this way once */ - if (cold_boot_done == false) { - prepare_cold_cpu(cpu); - cold_boot_done = true; + if (!per_cpu(cold_boot_done, cpu)) { + ret = func(cpu); + if (!ret) + per_cpu(cold_boot_done, cpu) = true; } /* @@ -99,39 +299,80 @@ static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle) */ spin_unlock(&boot_lock); - return 0; + return ret; } -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. The msm8x60 - * does not support the ARM SCU, so just set the possible cpu mask to - * NR_CPUS. - */ -static void __init qcom_smp_init_cpus(void) +static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle) { - unsigned int i, ncores = get_core_count(); + return qcom_boot_secondary(cpu, scss_release_secondary); +} - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } +static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + return qcom_boot_secondary(cpu, kpssv1_release_secondary); +} - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); +static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + return qcom_boot_secondary(cpu, kpssv2_release_secondary); } static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) { + int cpu, map; + unsigned int flags = 0; + static const int cold_boot_flags[] = { + 0, + SCM_FLAG_COLDBOOT_CPU1, + SCM_FLAG_COLDBOOT_CPU2, + SCM_FLAG_COLDBOOT_CPU3, + }; + + for_each_present_cpu(cpu) { + map = cpu_logical_map(cpu); + if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) { + set_cpu_present(cpu, false); + continue; + } + flags |= cold_boot_flags[map]; + } + + if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags)) { + for_each_present_cpu(cpu) { + if (cpu == smp_processor_id()) + continue; + set_cpu_present(cpu, false); + } + pr_warn("Failed to set CPU boot address, disabling SMP\n"); + } } -struct smp_operations qcom_smp_ops __initdata = { - .smp_init_cpus = qcom_smp_init_cpus, +static struct smp_operations smp_msm8660_ops __initdata = { + .smp_prepare_cpus = qcom_smp_prepare_cpus, + .smp_secondary_init = qcom_secondary_init, + .smp_boot_secondary = msm8660_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = qcom_cpu_die, +#endif +}; +CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops); + +static struct smp_operations qcom_smp_kpssv1_ops __initdata = { + .smp_prepare_cpus = qcom_smp_prepare_cpus, + .smp_secondary_init = qcom_secondary_init, + .smp_boot_secondary = kpssv1_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = qcom_cpu_die, +#endif +}; +CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops); + +static struct smp_operations qcom_smp_kpssv2_ops __initdata = { .smp_prepare_cpus = qcom_smp_prepare_cpus, .smp_secondary_init = qcom_secondary_init, - .smp_boot_secondary = qcom_boot_secondary, + .smp_boot_secondary = kpssv2_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = qcom_cpu_die, #endif }; +CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops); diff --git a/arch/arm/mach-qcom/scm-boot.h b/arch/arm/mach-qcom/scm-boot.h index 7be32ff5d687..6aabb2428176 100644 --- a/arch/arm/mach-qcom/scm-boot.h +++ b/arch/arm/mach-qcom/scm-boot.h @@ -13,9 +13,11 @@ #define __MACH_SCM_BOOT_H #define SCM_BOOT_ADDR 0x1 -#define SCM_FLAG_COLDBOOT_CPU1 0x1 -#define SCM_FLAG_WARMBOOT_CPU1 0x2 -#define SCM_FLAG_WARMBOOT_CPU0 0x4 +#define SCM_FLAG_COLDBOOT_CPU1 0x01 +#define SCM_FLAG_COLDBOOT_CPU2 0x08 +#define SCM_FLAG_COLDBOOT_CPU3 0x20 +#define SCM_FLAG_WARMBOOT_CPU0 0x04 +#define SCM_FLAG_WARMBOOT_CPU1 0x02 int scm_set_boot_addr(phys_addr_t addr, int flags); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6b2f58645a73..1caee6d548b8 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -5,6 +5,7 @@ config ARCH_ROCKCHIP select ARCH_REQUIRE_GPIOLIB select ARM_GIC select CACHE_L2X0 + select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select DW_APB_TIMER_OF select ARM_GLOBAL_TIMER diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 1547d4fc920a..4377a1436a98 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o +obj-$(CONFIG_SMP) += headsmp.o platsmp.o diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h new file mode 100644 index 000000000000..e2e7c9dbb200 --- /dev/null +++ b/arch/arm/mach-rockchip/core.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +extern char rockchip_secondary_trampoline; +extern char rockchip_secondary_trampoline_end; + +extern unsigned long rockchip_boot_fn; +extern void rockchip_secondary_startup(void); + +extern struct smp_operations rockchip_smp_ops; diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S new file mode 100644 index 000000000000..73206e360e31 --- /dev/null +++ b/arch/arm/mach-rockchip/headsmp.S @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/linkage.h> +#include <linux/init.h> + +ENTRY(rockchip_secondary_startup) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(rockchip_secondary_startup) + +ENTRY(rockchip_secondary_trampoline) + ldr pc, 1f +ENDPROC(rockchip_secondary_trampoline) + .globl rockchip_boot_fn +rockchip_boot_fn: +1: .space 4 + +ENTRY(rockchip_secondary_trampoline_end) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c new file mode 100644 index 000000000000..dbfa5a26cfff --- /dev/null +++ b/arch/arm/mach-rockchip/platsmp.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/smp.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#include <asm/cacheflush.h> +#include <asm/smp_scu.h> +#include <asm/smp_plat.h> +#include <asm/mach/map.h> + +#include "core.h" + +static void __iomem *scu_base_addr; +static void __iomem *sram_base_addr; +static int ncores; + +#define PMU_PWRDN_CON 0x08 +#define PMU_PWRDN_ST 0x0c + +#define PMU_PWRDN_SCU 4 + +static void __iomem *pmu_base_addr; + +static inline bool pmu_power_domain_is_on(int pd) +{ + return !(readl_relaxed(pmu_base_addr + PMU_PWRDN_ST) & BIT(pd)); +} + +static void pmu_set_power_domain(int pd, bool on) +{ + u32 val = readl_relaxed(pmu_base_addr + PMU_PWRDN_CON); + if (on) + val &= ~BIT(pd); + else + val |= BIT(pd); + writel(val, pmu_base_addr + PMU_PWRDN_CON); + + while (pmu_power_domain_is_on(pd) != on) { } +} + +/* + * Handling of CPU cores + */ + +static int __cpuinit rockchip_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + if (!sram_base_addr || !pmu_base_addr) { + pr_err("%s: sram or pmu missing for cpu boot\n", __func__); + return -ENXIO; + } + + if (cpu >= ncores) { + pr_err("%s: cpu %d outside maximum number of cpus %d\n", + __func__, cpu, ncores); + return -ENXIO; + } + + /* start the core */ + pmu_set_power_domain(0 + cpu, true); + + return 0; +} + +/** + * rockchip_smp_prepare_sram - populate necessary sram block + * Starting cores execute the code residing at the start of the on-chip sram + * after power-on. Therefore make sure, this sram region is reserved and + * big enough. After this check, copy the trampoline code that directs the + * core to the real startup code in ram into the sram-region. + * @node: mmio-sram device node + */ +static int __init rockchip_smp_prepare_sram(struct device_node *node) +{ + unsigned int trampoline_sz = &rockchip_secondary_trampoline_end - + &rockchip_secondary_trampoline; + struct resource res; + unsigned int rsize; + int ret; + + ret = of_address_to_resource(node, 0, &res); + if (ret < 0) { + pr_err("%s: could not get address for node %s\n", + __func__, node->full_name); + return ret; + } + + rsize = resource_size(&res); + if (rsize < trampoline_sz) { + pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n", + __func__, rsize, trampoline_sz); + return -EINVAL; + } + + sram_base_addr = of_iomap(node, 0); + + /* set the boot function for the sram code */ + rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup); + + /* copy the trampoline to sram, that runs during startup of the core */ + memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz); + flush_cache_all(); + outer_clean_range(0, trampoline_sz); + + dsb_sev(); + + return 0; +} + +static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + unsigned int i; + + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (!node) { + pr_err("%s: missing scu\n", __func__); + return; + } + + scu_base_addr = of_iomap(node, 0); + if (!scu_base_addr) { + pr_err("%s: could not map scu registers\n", __func__); + return; + } + + node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram"); + if (!node) { + pr_err("%s: could not find sram dt node\n", __func__); + return; + } + + if (rockchip_smp_prepare_sram(node)) + return; + + node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu"); + if (!node) { + pr_err("%s: could not find sram dt node\n", __func__); + return; + } + + pmu_base_addr = of_iomap(node, 0); + if (!pmu_base_addr) { + pr_err("%s: could not map pmu registers\n", __func__); + return; + } + + /* enable the SCU power domain */ + pmu_set_power_domain(PMU_PWRDN_SCU, true); + + /* + * While the number of cpus is gathered from dt, also get the number + * of cores from the scu to verify this value when booting the cores. + */ + ncores = scu_get_core_count(scu_base_addr); + + scu_enable(scu_base_addr); + + /* Make sure that all cores except the first are really off */ + for (i = 1; i < ncores; i++) + pmu_set_power_domain(0 + i, false); +} + +struct smp_operations rockchip_smp_ops __initdata = { + .smp_prepare_cpus = rockchip_smp_prepare_cpus, + .smp_boot_secondary = rockchip_boot_secondary, +}; diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 82c0b0709712..d211d6fa0d98 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -22,6 +22,7 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/hardware/cache-l2x0.h> +#include "core.h" static void __init rockchip_dt_init(void) { @@ -38,6 +39,7 @@ static const char * const rockchip_board_dt_compat[] = { }; DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") + .smp = smp_ops(rockchip_smp_ops), .init_machine = rockchip_dt_init, .dt_compat = rockchip_board_dt_compat, MACHINE_END diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index efd53848947d..c0b650b1c846 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -9,6 +9,7 @@ config ARCH_SHMOBILE_MULTI select HAVE_ARM_TWD if SMP select ARM_GIC select MIGHT_HAVE_PCI + select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE select NO_IOPORT select PINCTRL select ARCH_REQUIRE_GPIOLIB @@ -129,6 +130,7 @@ config ARCH_R8A7790 select SH_CLK_CPG select RENESAS_IRQC select SYS_SUPPORTS_SH_CMT + select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE config ARCH_R8A7791 bool "R-Car M2 (R8A77910)" @@ -139,6 +141,7 @@ config ARCH_R8A7791 select SH_CLK_CPG select RENESAS_IRQC select SYS_SUPPORTS_SH_CMT + select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE config ARCH_EMEV2 bool "Emma Mobile EV2" diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index fe7d4ff706e4..d38a6362e5f8 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -52,7 +52,8 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o pm-rmobile.o obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o pm-rmobile.o -obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o +obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o pm-rcar.o +obj-$(CONFIG_ARCH_R8A7790) += pm-r8a7790.o pm-rcar.o # Board objects ifdef CONFIG_ARCH_SHMOBILE_MULTI diff --git a/arch/arm/mach-shmobile/include/mach/pm-rcar.h b/arch/arm/mach-shmobile/include/mach/pm-rcar.h new file mode 100644 index 000000000000..ef3a1ef628f1 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/pm-rcar.h @@ -0,0 +1,15 @@ +#ifndef PM_RCAR_H +#define PM_RCAR_H + +struct rcar_sysc_ch { + unsigned long chan_offs; + unsigned int chan_bit; + unsigned int isr_bit; +}; + +int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch); +int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch); +bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch); +void __iomem *rcar_sysc_init(phys_addr_t base); + +#endif /* PM_RCAR_H */ diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index b40e13631f6a..88eeceaf1088 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -3,6 +3,7 @@ #include <linux/sh_clk.h> #include <linux/pm_domain.h> +#include <mach/pm-rcar.h> /* HPB-DMA slave IDs */ enum { @@ -11,18 +12,12 @@ enum { HPBDMA_SLAVE_SDHI0_RX, }; -struct r8a7779_pm_ch { - unsigned long chan_offs; - unsigned int chan_bit; - unsigned int isr_bit; -}; - struct r8a7779_pm_domain { struct generic_pm_domain genpd; - struct r8a7779_pm_ch ch; + struct rcar_sysc_ch ch; }; -static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d) +static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d) { return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; } @@ -41,8 +36,6 @@ extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); extern void r8a7779_pm_init(void); extern void r8a7779_register_twd(void); -extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch); -extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch); #ifdef CONFIG_PM extern void __init r8a7779_init_pm_domains(void); diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h index 5fbfa28b40b6..3389f0775def 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h @@ -7,6 +7,7 @@ void r8a7790_add_standard_devices(void); void r8a7790_add_dt_devices(void); void r8a7790_clock_init(void); void r8a7790_pinmux_init(void); +void r8a7790_pm_init(void); void r8a7790_init_early(void); extern struct smp_operations r8a7790_smp_ops; diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 1da5a72d9642..8cb641c00fdb 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -75,8 +75,7 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit) apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res)); apmu_cpus[cpu].bit = bit; - pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit, - res->start, resource_size(res)); + pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res); } static struct { diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c index d50a8e9b94a4..d6fe189b2df6 100644 --- a/arch/arm/mach-shmobile/pm-r8a7779.c +++ b/arch/arm/mach-shmobile/pm-r8a7779.c @@ -20,132 +20,22 @@ #include <linux/console.h> #include <asm/io.h> #include <mach/common.h> +#include <mach/pm-rcar.h> #include <mach/r8a7779.h> -static void __iomem *r8a7779_sysc_base; - /* SYSC */ -#define SYSCSR 0x00 -#define SYSCISR 0x04 -#define SYSCISCR 0x08 #define SYSCIER 0x0c #define SYSCIMR 0x10 -#define PWRSR0 0x40 -#define PWRSR1 0x80 -#define PWRSR2 0xc0 -#define PWRSR3 0x100 -#define PWRSR4 0x140 - -#define PWRSR_OFFS 0x00 -#define PWROFFCR_OFFS 0x04 -#define PWRONCR_OFFS 0x0c -#define PWRER_OFFS 0x14 - -#define SYSCSR_RETRIES 100 -#define SYSCSR_DELAY_US 1 - -#define SYSCISR_RETRIES 1000 -#define SYSCISR_DELAY_US 1 #if defined(CONFIG_PM) || defined(CONFIG_SMP) -static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */ - -static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch, - int sr_bit, int reg_offs) -{ - int k; - - for (k = 0; k < SYSCSR_RETRIES; k++) { - if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit)) - break; - udelay(SYSCSR_DELAY_US); - } - - if (k == SYSCSR_RETRIES) - return -EAGAIN; - - iowrite32(1 << r8a7779_ch->chan_bit, - r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs); - - return 0; -} - -static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch) -{ - return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS); -} - -static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch) -{ - return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS); -} - -static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch, - int (*on_off_fn)(struct r8a7779_pm_ch *)) -{ - unsigned int isr_mask = 1 << r8a7779_ch->isr_bit; - unsigned int chan_mask = 1 << r8a7779_ch->chan_bit; - unsigned int status; - unsigned long flags; - int ret = 0; - int k; - - spin_lock_irqsave(&r8a7779_sysc_lock, flags); - - iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); - - do { - ret = on_off_fn(r8a7779_ch); - if (ret) - goto out; - - status = ioread32(r8a7779_sysc_base + - r8a7779_ch->chan_offs + PWRER_OFFS); - } while (status & chan_mask); - - for (k = 0; k < SYSCISR_RETRIES; k++) { - if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask) - break; - udelay(SYSCISR_DELAY_US); - } - - if (k == SYSCISR_RETRIES) - ret = -EIO; - - iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); - - out: - spin_unlock_irqrestore(&r8a7779_sysc_lock, flags); - - pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n", - r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0), - ioread32(r8a7779_sysc_base + PWRSR1), - ioread32(r8a7779_sysc_base + PWRSR2), - ioread32(r8a7779_sysc_base + PWRSR3), - ioread32(r8a7779_sysc_base + PWRSR4), ret); - return ret; -} - -int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch) -{ - return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off); -} - -int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch) -{ - return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on); -} - static void __init r8a7779_sysc_init(void) { - r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE); - if (!r8a7779_sysc_base) - panic("unable to ioremap r8a7779 SYSC hardware block\n"); + void __iomem *base = rcar_sysc_init(0xffd85000); /* enable all interrupt sources, but do not use interrupt handler */ - iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER); - iowrite32(0, r8a7779_sysc_base + SYSCIMR); + iowrite32(0x0131000e, base + SYSCIER); + iowrite32(0, base + SYSCIMR); } #else /* CONFIG_PM || CONFIG_SMP */ @@ -158,24 +48,17 @@ static inline void r8a7779_sysc_init(void) {} static int pd_power_down(struct generic_pm_domain *genpd) { - return r8a7779_sysc_power_down(to_r8a7779_ch(genpd)); + return rcar_sysc_power_down(to_r8a7779_ch(genpd)); } static int pd_power_up(struct generic_pm_domain *genpd) { - return r8a7779_sysc_power_up(to_r8a7779_ch(genpd)); + return rcar_sysc_power_up(to_r8a7779_ch(genpd)); } static bool pd_is_off(struct generic_pm_domain *genpd) { - struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd); - unsigned int st; - - st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS); - if (st & (1 << r8a7779_ch->chan_bit)) - return true; - - return false; + return rcar_sysc_power_is_off(to_r8a7779_ch(genpd)); } static bool pd_active_wakeup(struct device *dev) diff --git a/arch/arm/mach-shmobile/pm-r8a7790.c b/arch/arm/mach-shmobile/pm-r8a7790.c new file mode 100644 index 000000000000..fc82839e2c2a --- /dev/null +++ b/arch/arm/mach-shmobile/pm-r8a7790.c @@ -0,0 +1,45 @@ +/* + * r8a7790 Power management support + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/kernel.h> +#include <asm/io.h> +#include <mach/pm-rcar.h> +#include <mach/r8a7790.h> + +/* SYSC */ +#define SYSCIER 0x0c +#define SYSCIMR 0x10 + +#if defined(CONFIG_SMP) + +static void __init r8a7790_sysc_init(void) +{ + void __iomem *base = rcar_sysc_init(0xe6180000); + + /* enable all interrupt sources, but do not use interrupt handler */ + iowrite32(0x0131000e, base + SYSCIER); + iowrite32(0, base + SYSCIMR); +} + +#else /* CONFIG_SMP */ + +static inline void r8a7790_sysc_init(void) {} + +#endif /* CONFIG_SMP */ + +void __init r8a7790_pm_init(void) +{ + static int once; + + if (!once++) + r8a7790_sysc_init(); +} diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c new file mode 100644 index 000000000000..1f465a12d1b1 --- /dev/null +++ b/arch/arm/mach-shmobile/pm-rcar.c @@ -0,0 +1,141 @@ +/* + * R-Car SYSC Power management support + * + * Copyright (C) 2014 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/mm.h> +#include <linux/spinlock.h> +#include <asm/io.h> +#include <mach/pm-rcar.h> + +/* SYSC */ +#define SYSCSR 0x00 +#define SYSCISR 0x04 +#define SYSCISCR 0x08 + +#define PWRSR_OFFS 0x00 +#define PWROFFCR_OFFS 0x04 +#define PWRONCR_OFFS 0x0c +#define PWRER_OFFS 0x14 + +#define SYSCSR_RETRIES 100 +#define SYSCSR_DELAY_US 1 + +#define SYSCISR_RETRIES 1000 +#define SYSCISR_DELAY_US 1 + +#if defined(CONFIG_PM) || defined(CONFIG_SMP) + +static void __iomem *rcar_sysc_base; +static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ + +static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch, + int sr_bit, int reg_offs) +{ + int k; + + for (k = 0; k < SYSCSR_RETRIES; k++) { + if (ioread32(rcar_sysc_base + SYSCSR) & (1 << sr_bit)) + break; + udelay(SYSCSR_DELAY_US); + } + + if (k == SYSCSR_RETRIES) + return -EAGAIN; + + iowrite32(1 << sysc_ch->chan_bit, + rcar_sysc_base + sysc_ch->chan_offs + reg_offs); + + return 0; +} + +static int rcar_sysc_pwr_off(struct rcar_sysc_ch *sysc_ch) +{ + return rcar_sysc_pwr_on_off(sysc_ch, 0, PWROFFCR_OFFS); +} + +static int rcar_sysc_pwr_on(struct rcar_sysc_ch *sysc_ch) +{ + return rcar_sysc_pwr_on_off(sysc_ch, 1, PWRONCR_OFFS); +} + +static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch, + int (*on_off_fn)(struct rcar_sysc_ch *)) +{ + unsigned int isr_mask = 1 << sysc_ch->isr_bit; + unsigned int chan_mask = 1 << sysc_ch->chan_bit; + unsigned int status; + unsigned long flags; + int ret = 0; + int k; + + spin_lock_irqsave(&rcar_sysc_lock, flags); + + iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); + + do { + ret = on_off_fn(sysc_ch); + if (ret) + goto out; + + status = ioread32(rcar_sysc_base + + sysc_ch->chan_offs + PWRER_OFFS); + } while (status & chan_mask); + + for (k = 0; k < SYSCISR_RETRIES; k++) { + if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask) + break; + udelay(SYSCISR_DELAY_US); + } + + if (k == SYSCISR_RETRIES) + ret = -EIO; + + iowrite32(isr_mask, rcar_sysc_base + SYSCISCR); + + out: + spin_unlock_irqrestore(&rcar_sysc_lock, flags); + + pr_debug("sysc power domain %d: %08x -> %d\n", + sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret); + return ret; +} + +int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch) +{ + return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_off); +} + +int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch) +{ + return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_on); +} + +bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch) +{ + unsigned int st; + + st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS); + if (st & (1 << sysc_ch->chan_bit)) + return true; + + return false; +} + +void __iomem *rcar_sysc_init(phys_addr_t base) +{ + rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE); + if (!rcar_sysc_base) + panic("unable to ioremap R-Car SYSC hardware block\n"); + + return rcar_sysc_base; +} + +#endif /* CONFIG_PM || CONFIG_SMP */ diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 69ccc6c6fd33..10604480f325 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -28,7 +28,7 @@ #define MODEMR 0xe6160060 -u32 __init rcar_gen2_read_mode_pins(void) +u32 rcar_gen2_read_mode_pins(void) { void __iomem *modemr = ioremap_nocache(MODEMR, 4); u32 mode; diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 627c1f0d9478..e7a3201473d0 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -24,6 +24,7 @@ #include <linux/io.h> #include <linux/delay.h> #include <mach/common.h> +#include <mach/pm-rcar.h> #include <mach/r8a7779.h> #include <asm/cacheflush.h> #include <asm/smp_plat.h> @@ -33,25 +34,25 @@ #define AVECR IOMEM(0xfe700040) #define R8A7779_SCU_BASE 0xf0000000 -static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { +static struct rcar_sysc_ch r8a7779_ch_cpu1 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ .chan_bit = 1, /* ARM1 */ .isr_bit = 1, /* ARM1 */ }; -static struct r8a7779_pm_ch r8a7779_ch_cpu2 = { +static struct rcar_sysc_ch r8a7779_ch_cpu2 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ .chan_bit = 2, /* ARM2 */ .isr_bit = 2, /* ARM2 */ }; -static struct r8a7779_pm_ch r8a7779_ch_cpu3 = { +static struct rcar_sysc_ch r8a7779_ch_cpu3 = { .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ .chan_bit = 3, /* ARM3 */ .isr_bit = 3, /* ARM3 */ }; -static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { +static struct rcar_sysc_ch *r8a7779_ch_cpu[4] = { [1] = &r8a7779_ch_cpu1, [2] = &r8a7779_ch_cpu2, [3] = &r8a7779_ch_cpu3, @@ -67,7 +68,7 @@ void __init r8a7779_register_twd(void) static int r8a7779_platform_cpu_kill(unsigned int cpu) { - struct r8a7779_pm_ch *ch = NULL; + struct rcar_sysc_ch *ch = NULL; int ret = -EIO; cpu = cpu_logical_map(cpu); @@ -76,14 +77,14 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) ch = r8a7779_ch_cpu[cpu]; if (ch) - ret = r8a7779_sysc_power_down(ch); + ret = rcar_sysc_power_down(ch); return ret ? ret : 1; } static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) { - struct r8a7779_pm_ch *ch = NULL; + struct rcar_sysc_ch *ch = NULL; unsigned int lcpu = cpu_logical_map(cpu); int ret; @@ -91,7 +92,7 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) ch = r8a7779_ch_cpu[lcpu]; if (ch) - ret = r8a7779_sysc_power_up(ch); + ret = rcar_sysc_power_up(ch); else ret = -EIO; diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c index 015e2753de1f..591052799e8f 100644 --- a/arch/arm/mach-shmobile/smp-r8a7790.c +++ b/arch/arm/mach-shmobile/smp-r8a7790.c @@ -19,6 +19,8 @@ #include <linux/io.h> #include <asm/smp_plat.h> #include <mach/common.h> +#include <mach/pm-rcar.h> +#include <mach/r8a7790.h> #define RST 0xe6160000 #define CA15BAR 0x0020 @@ -27,6 +29,16 @@ #define CA7RESCNT 0x0044 #define MERAM 0xe8080000 +static struct rcar_sysc_ch r8a7790_ca15_scu = { + .chan_offs = 0x180, /* PWRSR5 .. PWRER5 */ + .isr_bit = 12, /* CA15-SCU */ +}; + +static struct rcar_sysc_ch r8a7790_ca7_scu = { + .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */ + .isr_bit = 21, /* CA7-SCU */ +}; + static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus) { void __iomem *p; @@ -54,6 +66,11 @@ static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus) writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000, p + CA7RESCNT); iounmap(p); + + /* turn on power to SCU */ + r8a7790_pm_init(); + rcar_sysc_power_up(&r8a7790_ca15_scu); + rcar_sysc_power_up(&r8a7790_ca7_scu); } struct smp_operations r8a7790_smp_ops __initdata = { diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 9de27cfa688f..b57d7d53b9d3 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -6,6 +6,7 @@ config ARCH_SUNXI select ARM_PSCI select CLKSRC_MMIO select GENERIC_IRQ_CHIP + select HAVE_ARM_ARCH_TIMER select PINCTRL select PINCTRL_SUNXI select RESET_CONTROLLER diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index aeea6ceea725..460b5a4962ef 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -94,8 +94,8 @@ static void sun6i_restart(enum reboot_mode mode, const char *cmd) } static struct of_device_id sunxi_restart_ids[] = { - { .compatible = "allwinner,sun4i-wdt" }, - { .compatible = "allwinner,sun6i-wdt" }, + { .compatible = "allwinner,sun4i-a10-wdt" }, + { .compatible = "allwinner,sun6i-a31-wdt" }, { /*sentinel*/ } }; diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 019bb1758662..6fbfbb77dcd9 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -14,7 +14,6 @@ obj-y += sleep.o obj-y += tegra.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o ifeq ($(CONFIG_CPU_IDLE),y) diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index e0b87300243d..b5fb7c110c64 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c @@ -19,6 +19,7 @@ #include <linux/cpuidle.h> #include <linux/cpu_pm.h> #include <linux/clockchips.h> +#include <asm/firmware.h> #include <asm/cpuidle.h> #include <asm/suspend.h> @@ -45,7 +46,11 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev, clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu); - cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); + call_firmware_op(prepare_idle); + + /* Do suspend by ourselves if the firmware does not implement it */ + if (call_firmware_op(do_idle) == -ENOSYS) + cpu_suspend(0, tegra30_sleep_cpu_secondary_finish); clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu); diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index eb72ae709124..929d1046e2b4 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -114,7 +114,7 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle) /* Wait for the power to come up. */ timeout = jiffies + msecs_to_jiffies(100); - while (tegra_pmc_cpu_is_powered(cpu)) { + while (!tegra_pmc_cpu_is_powered(cpu)) { if (time_after(jiffies, timeout)) return -ETIMEDOUT; udelay(10); diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 3d0c537d9b94..4cefc5cd6bed 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -484,6 +484,7 @@ int tegra_io_rail_power_on(int id) return 0; } +EXPORT_SYMBOL(tegra_io_rail_power_on); int tegra_io_rail_power_off(int id) { @@ -511,3 +512,4 @@ int tegra_io_rail_power_off(int id) return 0; } +EXPORT_SYMBOL(tegra_io_rail_power_off); diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c deleted file mode 100644 index 3ae4a7f1a2fb..000000000000 --- a/arch/arm/mach-tegra/tegra2_emc.c +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright (C) 2011 Google, Inc. - * - * Author: - * Colin Cross <ccross@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/platform_data/tegra_emc.h> - -#include "tegra2_emc.h" -#include "fuse.h" - -#ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE -static bool emc_enable = true; -#else -static bool emc_enable; -#endif -module_param(emc_enable, bool, 0644); - -static struct platform_device *emc_pdev; -static void __iomem *emc_regbase; - -static inline void emc_writel(u32 val, unsigned long addr) -{ - writel(val, emc_regbase + addr); -} - -static inline u32 emc_readl(unsigned long addr) -{ - return readl(emc_regbase + addr); -} - -static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = { - 0x2c, /* RC */ - 0x30, /* RFC */ - 0x34, /* RAS */ - 0x38, /* RP */ - 0x3c, /* R2W */ - 0x40, /* W2R */ - 0x44, /* R2P */ - 0x48, /* W2P */ - 0x4c, /* RD_RCD */ - 0x50, /* WR_RCD */ - 0x54, /* RRD */ - 0x58, /* REXT */ - 0x5c, /* WDV */ - 0x60, /* QUSE */ - 0x64, /* QRST */ - 0x68, /* QSAFE */ - 0x6c, /* RDV */ - 0x70, /* REFRESH */ - 0x74, /* BURST_REFRESH_NUM */ - 0x78, /* PDEX2WR */ - 0x7c, /* PDEX2RD */ - 0x80, /* PCHG2PDEN */ - 0x84, /* ACT2PDEN */ - 0x88, /* AR2PDEN */ - 0x8c, /* RW2PDEN */ - 0x90, /* TXSR */ - 0x94, /* TCKE */ - 0x98, /* TFAW */ - 0x9c, /* TRPAB */ - 0xa0, /* TCLKSTABLE */ - 0xa4, /* TCLKSTOP */ - 0xa8, /* TREFBW */ - 0xac, /* QUSE_EXTRA */ - 0x114, /* FBIO_CFG6 */ - 0xb0, /* ODT_WRITE */ - 0xb4, /* ODT_READ */ - 0x104, /* FBIO_CFG5 */ - 0x2bc, /* CFG_DIG_DLL */ - 0x2c0, /* DLL_XFORM_DQS */ - 0x2c4, /* DLL_XFORM_QUSE */ - 0x2e0, /* ZCAL_REF_CNT */ - 0x2e4, /* ZCAL_WAIT_CNT */ - 0x2a8, /* AUTO_CAL_INTERVAL */ - 0x2d0, /* CFG_CLKTRIM_0 */ - 0x2d4, /* CFG_CLKTRIM_1 */ - 0x2d8, /* CFG_CLKTRIM_2 */ -}; - -/* Select the closest EMC rate that is higher than the requested rate */ -long tegra_emc_round_rate(unsigned long rate) -{ - struct tegra_emc_pdata *pdata; - int i; - int best = -1; - unsigned long distance = ULONG_MAX; - - if (!emc_pdev) - return -EINVAL; - - pdata = emc_pdev->dev.platform_data; - - pr_debug("%s: %lu\n", __func__, rate); - - /* - * The EMC clock rate is twice the bus rate, and the bus rate is - * measured in kHz - */ - rate = rate / 2 / 1000; - - for (i = 0; i < pdata->num_tables; i++) { - if (pdata->tables[i].rate >= rate && - (pdata->tables[i].rate - rate) < distance) { - distance = pdata->tables[i].rate - rate; - best = i; - } - } - - if (best < 0) - return -EINVAL; - - pr_debug("%s: using %lu\n", __func__, pdata->tables[best].rate); - - return pdata->tables[best].rate * 2 * 1000; -} - -/* - * The EMC registers have shadow registers. When the EMC clock is updated - * in the clock controller, the shadow registers are copied to the active - * registers, allowing glitchless memory bus frequency changes. - * This function updates the shadow registers for a new clock frequency, - * and relies on the clock lock on the emc clock to avoid races between - * multiple frequency changes - */ -int tegra_emc_set_rate(unsigned long rate) -{ - struct tegra_emc_pdata *pdata; - int i; - int j; - - if (!emc_pdev) - return -EINVAL; - - pdata = emc_pdev->dev.platform_data; - - /* - * The EMC clock rate is twice the bus rate, and the bus rate is - * measured in kHz - */ - rate = rate / 2 / 1000; - - for (i = 0; i < pdata->num_tables; i++) - if (pdata->tables[i].rate == rate) - break; - - if (i >= pdata->num_tables) - return -EINVAL; - - pr_debug("%s: setting to %lu\n", __func__, rate); - - for (j = 0; j < TEGRA_EMC_NUM_REGS; j++) - emc_writel(pdata->tables[i].regs[j], emc_reg_addr[j]); - - emc_readl(pdata->tables[i].regs[TEGRA_EMC_NUM_REGS - 1]); - - return 0; -} - -#ifdef CONFIG_OF -static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np) -{ - struct device_node *iter; - u32 reg; - - for_each_child_of_node(np, iter) { - if (of_property_read_u32(iter, "nvidia,ram-code", ®)) - continue; - if (reg == tegra_bct_strapping) - return of_node_get(iter); - } - - return NULL; -} - -static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata( - struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *tnp, *iter; - struct tegra_emc_pdata *pdata; - int ret, i, num_tables; - - if (!np) - return NULL; - - if (of_find_property(np, "nvidia,use-ram-code", NULL)) { - tnp = tegra_emc_ramcode_devnode(np); - if (!tnp) - dev_warn(&pdev->dev, - "can't find emc table for ram-code 0x%02x\n", - tegra_bct_strapping); - } else - tnp = of_node_get(np); - - if (!tnp) - return NULL; - - num_tables = 0; - for_each_child_of_node(tnp, iter) - if (of_device_is_compatible(iter, "nvidia,tegra20-emc-table")) - num_tables++; - - if (!num_tables) { - pdata = NULL; - goto out; - } - - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); - pdata->tables = devm_kzalloc(&pdev->dev, - sizeof(*pdata->tables) * num_tables, - GFP_KERNEL); - - i = 0; - for_each_child_of_node(tnp, iter) { - u32 prop; - - ret = of_property_read_u32(iter, "clock-frequency", &prop); - if (ret) { - dev_err(&pdev->dev, "no clock-frequency in %s\n", - iter->full_name); - continue; - } - pdata->tables[i].rate = prop; - - ret = of_property_read_u32_array(iter, "nvidia,emc-registers", - pdata->tables[i].regs, - TEGRA_EMC_NUM_REGS); - if (ret) { - dev_err(&pdev->dev, - "malformed emc-registers property in %s\n", - iter->full_name); - continue; - } - - i++; - } - pdata->num_tables = i; - -out: - of_node_put(tnp); - return pdata; -} -#else -static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata( - struct platform_device *pdev) -{ - return NULL; -} -#endif - -static struct tegra_emc_pdata *tegra_emc_fill_pdata(struct platform_device *pdev) -{ - struct clk *c = clk_get_sys(NULL, "emc"); - struct tegra_emc_pdata *pdata; - unsigned long khz; - int i; - - WARN_ON(pdev->dev.platform_data); - BUG_ON(IS_ERR(c)); - - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); - pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables), - GFP_KERNEL); - - pdata->tables[0].rate = clk_get_rate(c) / 2 / 1000; - - for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) - pdata->tables[0].regs[i] = emc_readl(emc_reg_addr[i]); - - pdata->num_tables = 1; - - khz = pdata->tables[0].rate; - dev_info(&pdev->dev, "no tables provided, using %ld kHz emc, " - "%ld kHz mem\n", khz * 2, khz); - - return pdata; -} - -static int tegra_emc_probe(struct platform_device *pdev) -{ - struct tegra_emc_pdata *pdata; - struct resource *res; - - if (!emc_enable) { - dev_err(&pdev->dev, "disabled per module parameter\n"); - return -ENODEV; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - emc_regbase = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(emc_regbase)) - return PTR_ERR(emc_regbase); - - pdata = pdev->dev.platform_data; - - if (!pdata) - pdata = tegra_emc_dt_parse_pdata(pdev); - - if (!pdata) - pdata = tegra_emc_fill_pdata(pdev); - - pdev->dev.platform_data = pdata; - - emc_pdev = pdev; - - return 0; -} - -static struct of_device_id tegra_emc_of_match[] = { - { .compatible = "nvidia,tegra20-emc", }, - { }, -}; - -static struct platform_driver tegra_emc_driver = { - .driver = { - .name = "tegra-emc", - .owner = THIS_MODULE, - .of_match_table = tegra_emc_of_match, - }, - .probe = tegra_emc_probe, -}; - -static int __init tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -device_initcall(tegra_emc_init); diff --git a/arch/arm/mach-tegra/tegra2_emc.h b/arch/arm/mach-tegra/tegra2_emc.h deleted file mode 100644 index f61409b54cb7..000000000000 --- a/arch/arm/mach-tegra/tegra2_emc.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2011 Google, Inc. - * - * Author: - * Colin Cross <ccross@android.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_TEGRA2_EMC_H_ -#define __MACH_TEGRA_TEGRA2_EMC_H - -int tegra_emc_set_rate(unsigned long rate); -long tegra_emc_round_rate(unsigned long rate); - -#endif diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 241622e2fea3..f5ad9ee70426 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -854,7 +854,7 @@ config OUTER_CACHE_SYNC config CACHE_FEROCEON_L2 bool "Enable the Feroceon L2 cache controller" - depends on ARCH_KIRKWOOD || ARCH_MV78XX0 + depends on ARCH_KIRKWOOD || ARCH_MV78XX0 || ARCH_MVEBU default y select OUTER_CACHE help diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index aae891820f8f..dc814a548056 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -13,10 +13,15 @@ */ #include <linux/init.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <linux/highmem.h> +#include <linux/io.h> #include <asm/cacheflush.h> #include <asm/cp15.h> -#include <plat/cache-feroceon-l2.h> +#include <asm/hardware/cache-feroceon-l2.h> + +#define L2_WRITETHROUGH_KIRKWOOD BIT(4) /* * Low-level cache maintenance operations. @@ -352,3 +357,41 @@ void __init feroceon_l2_init(int __l2_wt_override) printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n", l2_wt_override ? ", in WT override mode" : ""); } +#ifdef CONFIG_OF +static const struct of_device_id feroceon_ids[] __initconst = { + { .compatible = "marvell,kirkwood-cache"}, + { .compatible = "marvell,feroceon-cache"}, + {} +}; + +int __init feroceon_of_init(void) +{ + struct device_node *node; + void __iomem *base; + bool l2_wt_override = false; + struct resource res; + +#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) + l2_wt_override = true; +#endif + + node = of_find_matching_node(NULL, feroceon_ids); + if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) { + if (of_address_to_resource(node, 0, &res)) + return -ENODEV; + + base = ioremap(res.start, resource_size(&res)); + if (!base) + return -ENOMEM; + + if (l2_wt_override) + writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base); + else + writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base); + } + + feroceon_l2_init(l2_wt_override); + + return 0; +} +#endif diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c index 1be0f4e5e6eb..b273739e6359 100644 --- a/arch/arm/mm/cache-tauros2.c +++ b/arch/arm/mm/cache-tauros2.c @@ -33,7 +33,7 @@ * outer cache operations into the kernel image if the kernel has been * configured to support a pre-v7 CPU. */ -#if __LINUX_ARM_ARCH__ < 7 +#ifdef CONFIG_CPU_32v5 /* * Low-level cache maintenance operations. */ @@ -229,33 +229,6 @@ static void __init tauros2_internal_init(unsigned int features) } #endif -#ifdef CONFIG_CPU_32v6 - /* - * Check whether this CPU lacks support for the v7 hierarchical - * cache ops. (PJ4 is in its v6 personality mode if the MMFR3 - * register indicates no support for the v7 hierarchical cache - * ops.) - */ - if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) { - /* - * When Tauros2 is used in an ARMv6 system, the L2 - * enable bit is in the ARMv6 ARM-mandated position - * (bit [26] of the System Control Register). - */ - if (!(get_cr() & 0x04000000)) { - printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); - adjust_cr(0x04000000, 0x04000000); - } - - mode = "ARMv6"; - outer_cache.inv_range = tauros2_inv_range; - outer_cache.clean_range = tauros2_clean_range; - outer_cache.flush_range = tauros2_flush_range; - outer_cache.disable = tauros2_disable; - outer_cache.resume = tauros2_resume; - } -#endif - #ifdef CONFIG_CPU_32v7 /* * Check whether this CPU has support for the v7 hierarchical diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index 3ef58c8dbf11..f8ee13c7bf7b 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -11,6 +11,9 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/of_device.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/regmap.h> struct imx_weim_devtype { unsigned int cs_count; @@ -56,6 +59,55 @@ static const struct of_device_id weim_id_table[] = { }; MODULE_DEVICE_TABLE(of, weim_id_table); +static int __init imx_weim_gpr_setup(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct property *prop; + const __be32 *p; + struct regmap *gpr; + u32 gprvals[4] = { + 05, /* CS0(128M) CS1(0M) CS2(0M) CS3(0M) */ + 033, /* CS0(64M) CS1(64M) CS2(0M) CS3(0M) */ + 0113, /* CS0(64M) CS1(32M) CS2(32M) CS3(0M) */ + 01111, /* CS0(32M) CS1(32M) CS2(32M) CS3(32M) */ + }; + u32 gprval = 0; + u32 val; + int cs = 0; + int i = 0; + + gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr"); + if (IS_ERR(gpr)) { + dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n"); + return 0; + } + + of_property_for_each_u32(np, "ranges", prop, p, val) { + if (i % 4 == 0) { + cs = val; + } else if (i % 4 == 3 && val) { + val = (val / SZ_32M) | 1; + gprval |= val << cs * 3; + } + i++; + } + + if (i == 0 || i % 4) + goto err; + + for (i = 0; i < ARRAY_SIZE(gprvals); i++) { + if (gprval == gprvals[i]) { + /* Found it. Set up IOMUXC_GPR1[11:0] with it. */ + regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gprval); + return 0; + } + } + +err: + dev_err(&pdev->dev, "Invalid 'ranges' configuration\n"); + return -EINVAL; +} + /* Parse and set the timing for this device. */ static int __init weim_timing_setup(struct device_node *np, void __iomem *base, const struct imx_weim_devtype *devtype) @@ -92,6 +144,12 @@ static int __init weim_parse_dt(struct platform_device *pdev, struct device_node *child; int ret; + if (devtype == &imx50_weim_devtype) { + ret = imx_weim_gpr_setup(pdev); + if (ret) + return ret; + } + for_each_child_of_node(pdev->dev.of_node, child) { if (!child->name) continue; diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 61ffdca96e25..ec42d2decb2f 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -39,6 +39,14 @@ config IMGPDC_IRQ select GENERIC_IRQ_CHIP select IRQ_DOMAIN +config CLPS711X_IRQCHIP + bool + depends on ARCH_CLPS711X + select IRQ_DOMAIN + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + default y + config ORION_IRQCHIP bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 1c0c151d108c..6cee9efa26e7 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o +obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o diff --git a/drivers/irqchip/irq-clps711x.c b/drivers/irqchip/irq-clps711x.c new file mode 100644 index 000000000000..33340dc97d1d --- /dev/null +++ b/drivers/irqchip/irq-clps711x.c @@ -0,0 +1,243 @@ +/* + * CLPS711X IRQ driver + * + * Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/irqdomain.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/slab.h> + +#include <asm/exception.h> +#include <asm/mach/irq.h> + +#include "irqchip.h" + +#define CLPS711X_INTSR1 (0x0240) +#define CLPS711X_INTMR1 (0x0280) +#define CLPS711X_BLEOI (0x0600) +#define CLPS711X_MCEOI (0x0640) +#define CLPS711X_TEOI (0x0680) +#define CLPS711X_TC1EOI (0x06c0) +#define CLPS711X_TC2EOI (0x0700) +#define CLPS711X_RTCEOI (0x0740) +#define CLPS711X_UMSEOI (0x0780) +#define CLPS711X_COEOI (0x07c0) +#define CLPS711X_INTSR2 (0x1240) +#define CLPS711X_INTMR2 (0x1280) +#define CLPS711X_SRXEOF (0x1600) +#define CLPS711X_KBDEOI (0x1700) +#define CLPS711X_INTSR3 (0x2240) +#define CLPS711X_INTMR3 (0x2280) + +static const struct { +#define CLPS711X_FLAG_EN (1 << 0) +#define CLPS711X_FLAG_FIQ (1 << 1) + unsigned int flags; + phys_addr_t eoi; +} clps711x_irqs[] = { + [1] = { CLPS711X_FLAG_FIQ, CLPS711X_BLEOI, }, + [3] = { CLPS711X_FLAG_FIQ, CLPS711X_MCEOI, }, + [4] = { CLPS711X_FLAG_EN, CLPS711X_COEOI, }, + [5] = { CLPS711X_FLAG_EN, }, + [6] = { CLPS711X_FLAG_EN, }, + [7] = { CLPS711X_FLAG_EN, }, + [8] = { CLPS711X_FLAG_EN, CLPS711X_TC1EOI, }, + [9] = { CLPS711X_FLAG_EN, CLPS711X_TC2EOI, }, + [10] = { CLPS711X_FLAG_EN, CLPS711X_RTCEOI, }, + [11] = { CLPS711X_FLAG_EN, CLPS711X_TEOI, }, + [12] = { CLPS711X_FLAG_EN, }, + [13] = { CLPS711X_FLAG_EN, }, + [14] = { CLPS711X_FLAG_EN, CLPS711X_UMSEOI, }, + [15] = { CLPS711X_FLAG_EN, CLPS711X_SRXEOF, }, + [16] = { CLPS711X_FLAG_EN, CLPS711X_KBDEOI, }, + [17] = { CLPS711X_FLAG_EN, }, + [18] = { CLPS711X_FLAG_EN, }, + [28] = { CLPS711X_FLAG_EN, }, + [29] = { CLPS711X_FLAG_EN, }, + [32] = { CLPS711X_FLAG_FIQ, }, +}; + +static struct { + void __iomem *base; + void __iomem *intmr[3]; + void __iomem *intsr[3]; + struct irq_domain *domain; + struct irq_domain_ops ops; +} *clps711x_intc; + +static asmlinkage void __exception_irq_entry clps711x_irqh(struct pt_regs *regs) +{ + u32 irqnr, irqstat; + + do { + irqstat = readw_relaxed(clps711x_intc->intmr[0]) & + readw_relaxed(clps711x_intc->intsr[0]); + if (irqstat) { + irqnr = irq_find_mapping(clps711x_intc->domain, + fls(irqstat) - 1); + handle_IRQ(irqnr, regs); + } + + irqstat = readw_relaxed(clps711x_intc->intmr[1]) & + readw_relaxed(clps711x_intc->intsr[1]); + if (irqstat) { + irqnr = irq_find_mapping(clps711x_intc->domain, + fls(irqstat) - 1 + 16); + handle_IRQ(irqnr, regs); + } + } while (irqstat); +} + +static void clps711x_intc_eoi(struct irq_data *d) +{ + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hwirq].eoi); +} + +static void clps711x_intc_mask(struct irq_data *d) +{ + irq_hw_number_t hwirq = irqd_to_hwirq(d); + void __iomem *intmr = clps711x_intc->intmr[hwirq / 16]; + u32 tmp; + + tmp = readl_relaxed(intmr); + tmp &= ~(1 << (hwirq % 16)); + writel_relaxed(tmp, intmr); +} + +static void clps711x_intc_unmask(struct irq_data *d) +{ + irq_hw_number_t hwirq = irqd_to_hwirq(d); + void __iomem *intmr = clps711x_intc->intmr[hwirq / 16]; + u32 tmp; + + tmp = readl_relaxed(intmr); + tmp |= 1 << (hwirq % 16); + writel_relaxed(tmp, intmr); +} + +static struct irq_chip clps711x_intc_chip = { + .name = "clps711x-intc", + .irq_eoi = clps711x_intc_eoi, + .irq_mask = clps711x_intc_mask, + .irq_unmask = clps711x_intc_unmask, +}; + +static int __init clps711x_intc_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + irq_flow_handler_t handler = handle_level_irq; + unsigned int flags = IRQF_VALID | IRQF_PROBE; + + if (!clps711x_irqs[hw].flags) + return 0; + + if (clps711x_irqs[hw].flags & CLPS711X_FLAG_FIQ) { + handler = handle_bad_irq; + flags |= IRQF_NOAUTOEN; + } else if (clps711x_irqs[hw].eoi) { + handler = handle_fasteoi_irq; + } + + /* Clear down pending interrupt */ + if (clps711x_irqs[hw].eoi) + writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hw].eoi); + + irq_set_chip_and_handler(virq, &clps711x_intc_chip, handler); + set_irq_flags(virq, flags); + + return 0; +} + +static int __init _clps711x_intc_init(struct device_node *np, + phys_addr_t base, resource_size_t size) +{ + int err; + + clps711x_intc = kzalloc(sizeof(*clps711x_intc), GFP_KERNEL); + if (!clps711x_intc) + return -ENOMEM; + + clps711x_intc->base = ioremap(base, size); + if (!clps711x_intc->base) { + err = -ENOMEM; + goto out_kfree; + } + + clps711x_intc->intsr[0] = clps711x_intc->base + CLPS711X_INTSR1; + clps711x_intc->intmr[0] = clps711x_intc->base + CLPS711X_INTMR1; + clps711x_intc->intsr[1] = clps711x_intc->base + CLPS711X_INTSR2; + clps711x_intc->intmr[1] = clps711x_intc->base + CLPS711X_INTMR2; + clps711x_intc->intsr[2] = clps711x_intc->base + CLPS711X_INTSR3; + clps711x_intc->intmr[2] = clps711x_intc->base + CLPS711X_INTMR3; + + /* Mask all interrupts */ + writel_relaxed(0, clps711x_intc->intmr[0]); + writel_relaxed(0, clps711x_intc->intmr[1]); + writel_relaxed(0, clps711x_intc->intmr[2]); + + err = irq_alloc_descs(-1, 0, ARRAY_SIZE(clps711x_irqs), numa_node_id()); + if (IS_ERR_VALUE(err)) + goto out_iounmap; + + clps711x_intc->ops.map = clps711x_intc_irq_map; + clps711x_intc->ops.xlate = irq_domain_xlate_onecell; + clps711x_intc->domain = + irq_domain_add_legacy(np, ARRAY_SIZE(clps711x_irqs), + 0, 0, &clps711x_intc->ops, NULL); + if (!clps711x_intc->domain) { + err = -ENOMEM; + goto out_irqfree; + } + + irq_set_default_host(clps711x_intc->domain); + set_handle_irq(clps711x_irqh); + +#ifdef CONFIG_FIQ + init_FIQ(0); +#endif + + return 0; + +out_irqfree: + irq_free_descs(0, ARRAY_SIZE(clps711x_irqs)); + +out_iounmap: + iounmap(clps711x_intc->base); + +out_kfree: + kfree(clps711x_intc); + + return err; +} + +void __init clps711x_intc_init(phys_addr_t base, resource_size_t size) +{ + BUG_ON(_clps711x_intc_init(NULL, base, size)); +} + +#ifdef CONFIG_IRQCHIP +static int __init clps711x_intc_init_dt(struct device_node *np, + struct device_node *parent) +{ + struct resource res; + int err; + + err = of_address_to_resource(np, 0, &res); + if (err) + return err; + + return _clps711x_intc_init(np, res.start, resource_size(&res)); +} +IRQCHIP_DECLARE(clps711x, "cirrus,clps711x-intc", clps711x_intc_init_dt); +#endif diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index f10f64fcc815..146e4fffd710 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -177,6 +177,15 @@ #define RESERVEDMEM_OF_TABLES() #endif +#ifdef CONFIG_SMP +#define CPU_METHOD_OF_TABLES() . = ALIGN(8); \ + VMLINUX_SYMBOL(__cpu_method_of_table_begin) = .; \ + *(__cpu_method_of_table) \ + VMLINUX_SYMBOL(__cpu_method_of_table_end) = .; +#else +#define CPU_METHOD_OF_TABLES() +#endif + #define KERNEL_DTB() \ STRUCT_ALIGN(); \ VMLINUX_SYMBOL(__dtb_start) = .; \ @@ -502,6 +511,7 @@ CLK_OF_TABLES() \ RESERVEDMEM_OF_TABLES() \ CLKSRC_OF_TABLES() \ + CPU_METHOD_OF_TABLES() \ KERNEL_DTB() \ IRQCHIP_OF_MATCH_TABLE() diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index 866e355fa409..ff44374a1a4e 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -242,6 +242,24 @@ #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) +#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) +#define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK (0xf << 8) +#define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK (0xf << 12) +#define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK (0xf << 16) +#define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK (0xf << 20) +#define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK (0xf << 24) +#define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK (0xf << 28) + +#define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK (0xf << 0) +#define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK (0xf << 4) +#define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK (0xf << 8) +#define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK (0xf << 12) +#define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK (0xf << 16) +#define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK (0xf << 20) +#define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK (0xf << 24) +#define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK (0xf << 28) + #define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) #define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) #define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) |