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| author | Stefan Riedmueller <s.riedmueller@phytec.de> | 2019-07-09 09:19:25 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-07-23 13:38:37 +0800 |
| commit | f638e7fdbfdfd4411a917beff761720f97feff7f (patch) | |
| tree | b4f32ee52b5b684d339eee579b560a31ddb9d314 | |
| parent | b349580a4caef6f1fc23c0bd5393d3557ccf467a (diff) | |
| download | lwn-f638e7fdbfdfd4411a917beff761720f97feff7f.tar.gz lwn-f638e7fdbfdfd4411a917beff761720f97feff7f.zip | |
ARM: dts: imx6ul: segin: Move ECSPI interface to board include file
The ECSPI interface is available on the expansion connector of every
PHYTEC phyBOARD-Segin. Move its definition to the board include file
for better reuse.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 14 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 16 |
2 files changed, 16 insertions, 14 deletions
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts index c6ef13685a7c..32d90c67a6f2 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -28,9 +28,6 @@ }; &ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -93,14 +90,3 @@ &usdhc1 { status = "okay"; }; - -&iomuxc { - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 - MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 - MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 7cd24ec40c36..8d5f8dc6ad58 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -103,6 +103,13 @@ assigned-clock-rates = <786432000>; }; +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; @@ -225,6 +232,15 @@ >; }; + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 |