diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2023-05-17 12:41:17 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@microchip.com> | 2023-05-22 16:00:34 +0300 |
| commit | f4f15c5cdc289db798ab0bf32fe83a6701946ef9 (patch) | |
| tree | 9d25caa6fba99b5d10ec7584a6602d46136269ab | |
| parent | d08f92bdfb2dc4a2a14237cfd8a22c568781797c (diff) | |
| download | lwn-f4f15c5cdc289db798ab0bf32fe83a6701946ef9.tar.gz lwn-f4f15c5cdc289db798ab0bf32fe83a6701946ef9.zip | |
ARM: dts: at91: at91sam9n12: witch sckc to new clock bindings
Switch slow clock controller to new clock bindings.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20230517094119.2894220-4-claudiu.beznea@microchip.com
| -rw-r--r-- | arch/arm/boot/dts/at91sam9n12.dtsi | 23 |
1 files changed, 3 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index c2e7460fb7ff..0e28101b26bf 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -146,28 +146,11 @@ clocks = <&clk32k>; }; - sckc@fffffe50 { + clk32k: clock-controller@fffffe50 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xfffffe50 0x4>; - - slow_osc: slow_osc { - compatible = "atmel,at91sam9x5-clk-slow-osc"; - #clock-cells = <0>; - clocks = <&slow_xtal>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9x5-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc>, <&slow_osc>; - }; + clocks = <&slow_xtal>; + #clock-cells = <0>; }; mmc0: mmc@f0008000 { |