diff options
| author | Christoph Niedermaier <cniedermaier@dh-electronics.com> | 2021-05-26 12:54:02 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-06-12 12:16:54 +0800 |
| commit | f4ab3f2848247caea9c760a5a598278413a0a953 (patch) | |
| tree | 268e4c462fbe08b2cbc5809847c6e002c4753ad3 | |
| parent | ab583173144a1f26daedc0caa616f397fe9ae411 (diff) | |
| download | lwn-f4ab3f2848247caea9c760a5a598278413a0a953.tar.gz lwn-f4ab3f2848247caea9c760a5a598278413a0a953.zip | |
ARM: dts: imx6q-dhcom: Add ethernet VIO regulator
Add VIO regulator that supplies multiple ethernet magnetics and
currently there is no upstream support for that in the networking,
so just keep the regulator enabled always to emulate what other
boards, which have this hard-wired, do. Until there is support.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index f4f5cf75de95..6b6842bee749 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -33,6 +33,19 @@ reg = <0x10000000 0x40000000>; }; + reg_eth_vio: regulator-eth-vio { + compatible = "regulator-fixed"; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_enet_vio>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_vio"; + vin-supply = <&sw2_reg>; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; @@ -280,6 +293,11 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1 + >; + }; + + pinctrl_enet_vio: enet-vio-grp { + fsl,pins = < MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0 >; }; |