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| author | Sam Protsenko <semen.protsenko@linaro.org> | 2023-02-22 22:21:30 -0600 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-03-06 16:57:15 +0100 |
| commit | f2819ea168ef6a66c6b91fc30ce659a030268add (patch) | |
| tree | 28deb79cd8f82bb672da8a2cf68acee8e38bf570 | |
| parent | ac409adafb5eb195a3c7f02a58509bf172d6c595 (diff) | |
| download | lwn-f2819ea168ef6a66c6b91fc30ce659a030268add.tar.gz lwn-f2819ea168ef6a66c6b91fc30ce659a030268add.zip | |
clk: samsung: clk-pll: Implement pll0818x PLL type
pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise,
pll0818x is the same as pll0822x. The only difference is:
- pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz)
- pl0818x is integer PLL with Low FVCO (600 to 1200 MHz)
Add pll0818x type as an alias to pll0822x.
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223042133.26551-4-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | drivers/clk/samsung/clk-pll.c | 1 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-pll.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5ceac4c25c1c..74934c6182ce 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1314,6 +1314,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_pll35xx_clk_ops; break; case pll_1417x: + case pll_0818x: case pll_0822x: pll->enable_offs = PLL0822X_ENABLE_SHIFT; pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 5d5a58d40e7e..0725d485c6ee 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -34,6 +34,7 @@ enum samsung_pll_type { pll_1451x, pll_1452x, pll_1460x, + pll_0818x, pll_0822x, pll_0831x, pll_142xx, |