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| author | Alexander Stein <alexander.stein@ew.tq-group.com> | 2022-06-13 14:33:52 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-06-19 16:53:24 +0800 |
| commit | edb67843983bbdf61b4c8c3c50618003d38bb4ae (patch) | |
| tree | fb909520d51dcac88fd48869b243426638d5517d | |
| parent | 5655699cf5cff9f4c4ee703792156bdd05d1addf (diff) | |
| download | lwn-edb67843983bbdf61b4c8c3c50618003d38bb4ae.tar.gz lwn-edb67843983bbdf61b4c8c3c50618003d38bb4ae.zip | |
ARM: dts: imx6ul: change operating-points to uint32-matrix
operating-points is a uint32-matrix as per opp-v1.yaml. Change it
accordingly. While at it, change fsl,soc-operating-points as well,
although there is no bindings file (yet). But they should have the same
format. Fixes the dt_binding_check warning:
cpu@0: operating-points:0: [696000, 1275000, 528000, 1175000, 396000,
1025000, 198000, 950000] is too long
cpu@0: operating-points:0: Additional items are not allowed (528000,
1175000, 396000, 1025000, 198000, 950000 were unexpected)
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/imx6ul.dtsi | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 97650709aaa3..d429243b1925 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -64,20 +64,18 @@ clock-frequency = <696000000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; - operating-points = < + operating-points = /* kHz uV */ - 696000 1275000 - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < + <696000 1275000>, + <528000 1175000>, + <396000 1025000>, + <198000 950000>; + fsl,soc-operating-points = /* KHz uV */ - 696000 1275000 - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; + <696000 1275000>, + <528000 1175000>, + <396000 1175000>, + <198000 1175000>; clocks = <&clks IMX6UL_CLK_ARM>, <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_PLL2_PFD2>, |