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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2022-05-08 18:57:11 +0100
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2022-06-14 11:53:19 +0100
commitecdef5b8317cdf18acb46223e087f04a226fa619 (patch)
treecf300c62bc46387ad3b9921831645fa4b96b3f53
parent732f2cb2fbb51bd5bc03a114bd102ab3b2f537fe (diff)
downloadlwn-ecdef5b8317cdf18acb46223e087f04a226fa619.tar.gz
lwn-ecdef5b8317cdf18acb46223e087f04a226fa619.zip
iio: temp: max31865: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition Fixes: e112dc4e18ea ("iio: temperature: Add MAX31865 RTD Support") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Navin Sankar Velliangiri <navin@linumiz.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-92-jic23@kernel.org
-rw-r--r--drivers/iio/temperature/max31865.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iio/temperature/max31865.c b/drivers/iio/temperature/max31865.c
index e3bb78184c6e..29e23652ba5a 100644
--- a/drivers/iio/temperature/max31865.c
+++ b/drivers/iio/temperature/max31865.c
@@ -55,7 +55,7 @@ struct max31865_data {
struct mutex lock;
bool filter_50hz;
bool three_wire;
- u8 buf[2] ____cacheline_aligned;
+ u8 buf[2] __aligned(IIO_DMA_MINALIGN);
};
static int max31865_read(struct max31865_data *data, u8 reg,