diff options
| author | James Hogan <james.hogan@imgtec.com> | 2015-01-27 21:45:51 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-03-31 12:04:12 +0200 |
| commit | ea3c023ebf7130d72f9f00a3992c22176ef6703b (patch) | |
| tree | b86ffe4183b99e17774d5cb5ff793779dbb8e840 | |
| parent | 7e3e6cb29aeb64df24a0325ffd18892eca33e9b4 (diff) | |
| download | lwn-ea3c023ebf7130d72f9f00a3992c22176ef6703b.tar.gz lwn-ea3c023ebf7130d72f9f00a3992c22176ef6703b.zip | |
IRQCHIP: mips-gic: Add missing definitions for FDC IRQ
Add missing VPE_PEND, VPE_RMASK and VPE_SMASK definitions for the local
FDC interrupt.
These local interrupt definitions aren't directly used, but if they
exist they should be complete.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9127/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | include/linux/irqchip/mips-gic.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h index e6a6aac451db..2e79b4bb2d75 100644 --- a/include/linux/irqchip/mips-gic.h +++ b/include/linux/irqchip/mips-gic.h @@ -165,6 +165,8 @@ #define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF) #define GIC_VPE_PEND_SWINT1_SHF 5 #define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF) +#define GIC_VPE_PEND_FDC_SHF 6 +#define GIC_VPE_PEND_FDC_MSK (MSK(1) << GIC_VPE_PEND_FDC_SHF) /* GIC_VPE_RMASK Masks */ #define GIC_VPE_RMASK_WD_SHF 0 @@ -179,6 +181,8 @@ #define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF) #define GIC_VPE_RMASK_SWINT1_SHF 5 #define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF) +#define GIC_VPE_RMASK_FDC_SHF 6 +#define GIC_VPE_RMASK_FDC_MSK (MSK(1) << GIC_VPE_RMASK_FDC_SHF) /* GIC_VPE_SMASK Masks */ #define GIC_VPE_SMASK_WD_SHF 0 @@ -193,6 +197,8 @@ #define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF) #define GIC_VPE_SMASK_SWINT1_SHF 5 #define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF) +#define GIC_VPE_SMASK_FDC_SHF 6 +#define GIC_VPE_SMASK_FDC_MSK (MSK(1) << GIC_VPE_SMASK_FDC_SHF) /* GIC nomenclature for Core Interrupt Pins. */ #define GIC_CPU_INT0 0 /* Core Interrupt 2 */ |