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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-05-08 18:56:07 +0100 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-06-14 11:53:14 +0100 |
| commit | e770f78036ce4327caf285873f4b20564a8b4f0f (patch) | |
| tree | 18f6e62a7a4ceed2f010eee9f5957cbff590357f | |
| parent | 9d7019e43ee67a48cef63f8f23f002233064d390 (diff) | |
| download | lwn-e770f78036ce4327caf285873f4b20564a8b4f0f.tar.gz lwn-e770f78036ce4327caf285873f4b20564a8b4f0f.zip | |
iio: adc: mcp320x: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Worth noting the fixes tag refers to the same issue being observed
on a platform that probably had only 64 byte cachelines.
Fixes: 0e81bc99a082 ("iio: mcp320x: Fix occasional incorrect readings")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Michael Welling <mwelling@ieee.org>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-28-jic23@kernel.org
| -rw-r--r-- | drivers/iio/adc/mcp320x.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iio/adc/mcp320x.c b/drivers/iio/adc/mcp320x.c index b4c69acb33e3..f3b81798b3c9 100644 --- a/drivers/iio/adc/mcp320x.c +++ b/drivers/iio/adc/mcp320x.c @@ -92,7 +92,7 @@ struct mcp320x { struct mutex lock; const struct mcp320x_chip_info *chip_info; - u8 tx_buf ____cacheline_aligned; + u8 tx_buf __aligned(IIO_DMA_MINALIGN); u8 rx_buf[4]; }; |