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| author | Christoph Hellwig <hch@lst.de> | 2022-05-16 14:29:43 +0200 |
|---|---|---|
| committer | Christoph Hellwig <hch@lst.de> | 2022-05-17 07:33:27 +0200 |
| commit | e626f37e657adbab2a7abe51480925891662a5f3 (patch) | |
| tree | b5f39fa78efcec0678b837bbf72dc829d5557471 | |
| parent | 93ba75c90524618ef2c20979b0e660b9d071f0e6 (diff) | |
| download | lwn-e626f37e657adbab2a7abe51480925891662a5f3.tar.gz lwn-e626f37e657adbab2a7abe51480925891662a5f3.zip | |
nvme: split the enum used for various register constants
Instead of having one big enum add one for each register or field.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
| -rw-r--r-- | include/linux/nvme.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/include/linux/nvme.h b/include/linux/nvme.h index bbabdc7600da..5f6d432fa06a 100644 --- a/include/linux/nvme.h +++ b/include/linux/nvme.h @@ -204,8 +204,9 @@ enum { NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, - NVME_CAP_CSS_NVM = 1 << 0, - NVME_CAP_CSS_CSI = 1 << 6, +}; + +enum { NVME_CSTS_RDY = 1 << 0, NVME_CSTS_CFS = 1 << 1, NVME_CSTS_NSSRO = 1 << 4, @@ -214,10 +215,18 @@ enum { NVME_CSTS_SHST_OCCUR = 1 << 2, NVME_CSTS_SHST_CMPLT = 2 << 2, NVME_CSTS_SHST_MASK = 3 << 2, +}; + +enum { NVME_CMBMSC_CRE = 1 << 0, NVME_CMBMSC_CMSE = 1 << 1, }; +enum { + NVME_CAP_CSS_NVM = 1 << 0, + NVME_CAP_CSS_CSI = 1 << 6, +}; + struct nvme_id_power_state { __le16 max_power; /* centiwatts */ __u8 rsvd2; |