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| author | Huqiang Qin <huqiang.qin@amlogic.com> | 2023-07-14 20:24:40 +0800 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2023-07-23 21:23:16 +0200 |
| commit | e55ef16b840f03749b290549ec3ffc4c07f550be (patch) | |
| tree | e549440959db5df8ca723229459a9645b5159a57 | |
| parent | 060f03e95454a0f4a1deff3e5f912e461ae0f0c5 (diff) | |
| download | lwn-e55ef16b840f03749b290549ec3ffc4c07f550be.tar.gz lwn-e55ef16b840f03749b290549ec3ffc4c07f550be.zip | |
dt-bindings: pinctrl: Add compatibles for Amlogic C3 SoCs
Add a new compatible name for Amlogic C3 pin controller, and add
a new dt-binding header file which document the detail pin names.
Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230714122441.3098337-2-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml | 1 | ||||
| -rw-r--r-- | include/dt-bindings/gpio/amlogic-c3-gpio.h | 72 |
2 files changed, 73 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml index 4cee220ab652..4e7a456ea4cc 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml @@ -15,6 +15,7 @@ allOf: properties: compatible: enum: + - amlogic,c3-periphs-pinctrl - amlogic,meson-a1-periphs-pinctrl - amlogic,meson-s4-periphs-pinctrl diff --git a/include/dt-bindings/gpio/amlogic-c3-gpio.h b/include/dt-bindings/gpio/amlogic-c3-gpio.h new file mode 100644 index 000000000000..75c8da6f505f --- /dev/null +++ b/include/dt-bindings/gpio/amlogic-c3-gpio.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Huqiang Qin <huqiang.qin@amlogic.com> + */ + +#ifndef _DT_BINDINGS_AMLOGIC_C3_GPIO_H +#define _DT_BINDINGS_AMLOGIC_C3_GPIO_H + +#define GPIOE_0 0 +#define GPIOE_1 1 +#define GPIOE_2 2 +#define GPIOE_3 3 +#define GPIOE_4 4 + +#define GPIOB_0 5 +#define GPIOB_1 6 +#define GPIOB_2 7 +#define GPIOB_3 8 +#define GPIOB_4 9 +#define GPIOB_5 10 +#define GPIOB_6 11 +#define GPIOB_7 12 +#define GPIOB_8 13 +#define GPIOB_9 14 +#define GPIOB_10 15 +#define GPIOB_11 16 +#define GPIOB_12 17 +#define GPIOB_13 18 +#define GPIOB_14 19 + +#define GPIOC_0 20 +#define GPIOC_1 21 +#define GPIOC_2 22 +#define GPIOC_3 23 +#define GPIOC_4 24 +#define GPIOC_5 25 +#define GPIOC_6 26 + +#define GPIOX_0 27 +#define GPIOX_1 28 +#define GPIOX_2 29 +#define GPIOX_3 30 +#define GPIOX_4 31 +#define GPIOX_5 32 +#define GPIOX_6 33 +#define GPIOX_7 34 +#define GPIOX_8 35 +#define GPIOX_9 36 +#define GPIOX_10 37 +#define GPIOX_11 38 +#define GPIOX_12 39 +#define GPIOX_13 40 + +#define GPIOD_0 41 +#define GPIOD_1 42 +#define GPIOD_2 43 +#define GPIOD_3 44 +#define GPIOD_4 45 +#define GPIOD_5 46 +#define GPIOD_6 47 + +#define GPIOA_0 48 +#define GPIOA_1 49 +#define GPIOA_2 50 +#define GPIOA_3 51 +#define GPIOA_4 52 +#define GPIOA_5 53 + +#define GPIO_TEST_N 54 + +#endif /* _DT_BINDINGS_AMLOGIC_C3_GPIO_H */ |