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| author | Petr Machata <petrm@nvidia.com> | 2023-12-14 14:19:05 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2023-12-15 10:58:00 +0000 |
| commit | d9d441e8e89db78683032bcedb74964575a8eafe (patch) | |
| tree | 5b5fa2e74e4d2d766ae161cffd3a15d573247dce | |
| parent | 523e1f5f3754fa738f2ab6eb6f4d2b6f51d10b83 (diff) | |
| download | lwn-d9d441e8e89db78683032bcedb74964575a8eafe.tar.gz lwn-d9d441e8e89db78683032bcedb74964575a8eafe.zip | |
mlxsw: reg: Add nve_flood_prf_id field to SFMR
The field is used for setting a flood profile for lookup of KVD entry for
NVE underlay. As the other uses of flood profile, this references a traffic
type-to-offset mapping, except here it is not applied to PGT offsets, but
KVD offsets.
Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/reg.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 3aae4467e431..8892654c685f 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -1954,6 +1954,15 @@ MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); */ MLXSW_ITEM32(reg, sfmr, cff_mid_base, 0x20, 0, 16); +/* reg_sfmr_nve_flood_prf_id + * FID flooding profile_id for NVE Encap + * Range 0..(max_cap_nve_flood_prf-1) + * Access: RW + * + * Note: Reserved when SwitchX/-2 and Spectrum-1 + */ +MLXSW_ITEM32(reg, sfmr, nve_flood_prf_id, 0x24, 8, 2); + /* reg_sfmr_cff_prf_id * Compressed Fid Flooding profile_id * Range 0..(max_cap_nve_flood_prf-1) |