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| author | Joe Konno <joe.konno@intel.com> | 2015-05-12 07:59:42 -0700 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2015-07-03 23:02:15 -0400 |
| commit | d36bec4cb0ae2ca617e9fba2c80467e9443f0d9c (patch) | |
| tree | 01e09f5fb618886bc9ef404547d6c5107de9364d | |
| parent | f5ef1e8cd9a703dcdc0c34aac0898e6d112a9a6e (diff) | |
| download | lwn-d36bec4cb0ae2ca617e9fba2c80467e9443f0d9c.tar.gz lwn-d36bec4cb0ae2ca617e9fba2c80467e9443f0d9c.zip | |
intel_pstate: set BYT MSR with wrmsrl_on_cpu()
[ Upstream commit 0dd23f94251f49da99a6cbfb22418b2d757d77d6 ]
Commit 007bea098b86 (intel_pstate: Add setting voltage value for
baytrail P states.) introduced byt_set_pstate() with the assumption that
it would always be run by the CPU whose MSR is to be written by it. It
turns out, however, that is not always the case in practice, so modify
byt_set_pstate() to enforce the MSR write done by it to always happen on
the right CPU.
Fixes: 007bea098b86 (intel_pstate: Add setting voltage value for baytrail P states.)
Signed-off-by: Joe Konno <joe.konno@intel.com>
Acked-by: Kristen Carlson Accardi <kristen@linux.intel.com>
Cc: 3.14+ <stable@vger.kernel.org> # 3.14+
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
| -rw-r--r-- | drivers/cpufreq/intel_pstate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 27bb6d3877ed..d0d21363c63f 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -443,7 +443,7 @@ static void byt_set_pstate(struct cpudata *cpudata, int pstate) val |= vid; - wrmsrl(MSR_IA32_PERF_CTL, val); + wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); } #define BYT_BCLK_FREQS 5 |