diff options
| author | Kan Liang <kan.liang@linux.intel.com> | 2020-09-28 05:30:42 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2020-09-29 09:57:02 +0200 |
| commit | c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9 (patch) | |
| tree | f412f9632a31930ff19f9e381a1159b4fc1945f5 | |
| parent | dbfd638889a0396f5fe14ff3cc2263ec1e1cac62 (diff) | |
| download | lwn-c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9.tar.gz lwn-c3bb8a9fa31b99f5b7d2e45cd0a10db91349f4c9.zip | |
perf/x86/msr: Add Jasper Lake support
The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of perf MSR, there is nothing changed compared with
Elkhart Lake.
Share the code path with Elkhart Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1601296242-32763-2-git-send-email-kan.liang@linux.intel.com
| -rw-r--r-- | arch/x86/events/msr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index a949f6f55991..4be8f9cabd07 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ATOM_GOLDMONT_PLUS: case INTEL_FAM6_ATOM_TREMONT_D: case INTEL_FAM6_ATOM_TREMONT: + case INTEL_FAM6_ATOM_TREMONT_L: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: |