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| author | Andreas Kemnade <andreas@kemnade.info> | 2021-09-24 11:14:36 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-10-05 13:45:29 +0800 |
| commit | bea74c43602a96f4cce05990a27f6f9fdb0405b2 (patch) | |
| tree | 327253305e2d6acd43e2904926a9bc8ea70ec8f9 | |
| parent | 31ffe01e8200f05041da519a7b371d02020a0ba3 (diff) | |
| download | lwn-bea74c43602a96f4cce05990a27f6f9fdb0405b2.tar.gz lwn-bea74c43602a96f4cce05990a27f6f9fdb0405b2.zip | |
ARM: dts: imx6sl: fixup of operating points
Make operating point definitions comply with binding
specifications.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/imx6sl.dtsi | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 997b96c1c47b..c7d907c5c352 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -55,18 +55,16 @@ device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; - operating-points = < + operating-points = /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < + <996000 1275000>, + <792000 1175000>, + <396000 975000>; + fsl,soc-operating-points = /* ARM kHz SOC-PU uV */ - 996000 1225000 - 792000 1175000 - 396000 1175000 - >; + <996000 1225000>, + <792000 1175000>, + <396000 1175000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, |