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| author | Paul Burton <paul.burton@mips.com> | 2019-10-01 21:53:41 +0000 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-10-07 09:43:08 -0700 |
| commit | ae4cd0b1a4756344cb99c0004d156b585cf9e907 (patch) | |
| tree | a14701a3331856a7b482b571a7861b64466006db | |
| parent | 7f56b123548142fd48b2c6891977e8fda695a838 (diff) | |
| download | lwn-ae4cd0b1a4756344cb99c0004d156b585cf9e907.tar.gz lwn-ae4cd0b1a4756344cb99c0004d156b585cf9e907.zip | |
MIPS: barrier: Make __smp_mb__before_atomic() a no-op for Loongson3
Loongson3 systems with CONFIG_CPU_LOONGSON3_WORKAROUNDS enabled already
emit a full completion barrier as part of the inline assembly containing
LL/SC loops for atomic operations. As such the barrier emitted by
__smp_mb__before_atomic() is redundant, and we can remove it.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
| -rw-r--r-- | arch/mips/include/asm/barrier.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index 6d92d5ccdafa..49ff172a72b9 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -119,7 +119,17 @@ static inline void wmb(void) #define nudge_writes() mb() #endif -#define __smp_mb__before_atomic() __smp_mb__before_llsc() +/* + * In the Loongson3 LL/SC workaround case, all of our LL/SC loops already have + * a completion barrier immediately preceding the LL instruction. Therefore we + * can skip emitting a barrier from __smp_mb__before_atomic(). + */ +#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS +# define __smp_mb__before_atomic() +#else +# define __smp_mb__before_atomic() __smp_mb__before_llsc() +#endif + #define __smp_mb__after_atomic() smp_llsc_mb() static inline void sync_ginv(void) |