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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-04-30 14:18:56 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-05-04 10:26:35 +0200 |
| commit | a93fbb002310ef04fce504dbf1510f6eb8265188 (patch) | |
| tree | f5c21139e522a4a27893fc7643638e99370286d4 | |
| parent | 2f00bb4a69c770b7957b9b4621323c2f84fc6538 (diff) | |
| download | lwn-a93fbb002310ef04fce504dbf1510f6eb8265188.tar.gz lwn-a93fbb002310ef04fce504dbf1510f6eb8265188.zip | |
arm64: dts: stratix10/agilex: drop useless 'dma-channels/requests' properties
The pl330 DMA controller provides number of DMA channels and requests
through its registers, so duplicating this information (with a chance of
mistakes) in DTS is pointless. Additionally the DTS used always wrong
property names which causes DT schema check failures - the bindings
documented 'dma-channels' and 'dma-requests' properties without leading
hash sign.
Reported-by: Rob Herring <robh@kernel.org>
Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220430121902.59895-4-krzysztof.kozlowski@linaro.org
| -rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 884bda106399..aa2bba75265f 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -346,8 +346,6 @@ <0 88 4>, <0 89 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index c78371703e76..caccb0334ada 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -350,8 +350,6 @@ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; reset-names = "dma", "dma-ocp"; clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; |