diff options
| author | Foryun Ma <foryun.ma@jaguarmicro.com> | 2024-06-04 11:21:51 +0800 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2024-07-17 10:35:08 -0700 |
| commit | a0328b397f3339d8d17a6ec356e94b3c110b010c (patch) | |
| tree | 0ae02a46630d221359620c94bacca74fcfb78de3 | |
| parent | 56478475560bde71dd3ef944b5013900272db273 (diff) | |
| download | lwn-a0328b397f3339d8d17a6ec356e94b3c110b010c.tar.gz lwn-a0328b397f3339d8d17a6ec356e94b3c110b010c.zip | |
cxl/core/pci: Move reading of control register to immediately before usage
Relocate the reading of the DVSEC control register to immediately
before usage and avoid unnecessary PCI config access from the read
if DVSEC capability check, hdm_count check, or device validity check
results in failure.
Signed-off-by: Foryun Ma <foryun.ma@jaguarmicro.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240604032151.655-1-foryun.ma@jaguarmicro.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
| -rw-r--r-- | drivers/cxl/core/pci.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 8567dd11eaac..a663e7566c48 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -338,10 +338,6 @@ int cxl_dvsec_rr_decode(struct device *dev, int d, if (rc) return rc; - rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); - if (rc) - return rc; - if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { dev_dbg(dev, "Not MEM Capable\n"); return -ENXIO; @@ -368,6 +364,10 @@ int cxl_dvsec_rr_decode(struct device *dev, int d, * disabled, and they will remain moot after the HDM Decoder * capability is enabled. */ + rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); + if (rc) + return rc; + info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); if (!info->mem_enabled) return 0; |