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| author | Vinod Govindapillai <vinod.govindapillai@intel.com> | 2023-10-01 14:31:53 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2023-10-11 13:54:34 +0300 |
| commit | 9a3acd8c77cdfbed6debf38c1abeea06d9113173 (patch) | |
| tree | ba18b2a459706dd86786afa87c8e56d05b811e0b | |
| parent | 55ce2c37cfb969b7d8bf4a1a5c7956ffada0cae8 (diff) | |
| download | lwn-9a3acd8c77cdfbed6debf38c1abeea06d9113173.tar.gz lwn-9a3acd8c77cdfbed6debf38c1abeea06d9113173.zip | |
drm/i915/xe2lpd: display capability register definitions
Register definitions to track the reported scalable display
feature configurations
Bspec: 71161
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231001113155.80659-2-vinod.govindapillai@intel.com
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1a9ca1e530bc..135e8d8dbdf0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4680,6 +4680,13 @@ #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) +#define XE2LPD_DE_CAP _MMIO(0x41100) +#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) +#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) +#define XE2LPD_DE_CAP_DSC_REMOVED 1 +#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26) +#define XE2LPD_DE_CAP_SCALER_SINGLE 1 + #define SKL_DSSM _MMIO(0x51004) #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) |