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| author | Michal Simek <michal.simek@amd.com> | 2023-08-03 09:22:56 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2023-08-09 13:21:48 +0200 |
| commit | 92b5b53380955e6ca3c5786c72dbc99dcdfa8e4f (patch) | |
| tree | e789eb4194e447f13928841b296375bb321f6405 | |
| parent | aa857326a454814478b8e7c52caeee1743d92e0d (diff) | |
| download | lwn-92b5b53380955e6ca3c5786c72dbc99dcdfa8e4f.tar.gz lwn-92b5b53380955e6ca3c5786c72dbc99dcdfa8e4f.zip | |
dt-bindings: mmc: arasan,sdci: Add power-domains and iommus properties
ZynqMP SDHCI Arasan IP core has own power domain and also iommu ID that's
why describe optional power-domains and iommus properties.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/bf912d5f5e74b43903a84262565f564bfe0fed7e.1691047370.git.michal.simek@amd.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index a6c19a6cc99e..3e99801f77d2 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -160,6 +160,12 @@ properties: description: The MIO bank number in which the command and data lines are configured. + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + dependencies: '#clock-cells': [ clock-output-names ] |