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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-08-15 20:22:23 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2020-08-24 14:15:36 -0700 |
| commit | 8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0 (patch) | |
| tree | 3ab8c37fef8c955af08b30999bd502a991e2b812 | |
| parent | 9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff) | |
| download | lwn-8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0.tar.gz lwn-8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0.zip | |
ARM: dts: meson: move the L2 cache-controller inside the SoC node
All IO mapped SoC peripherals should be within the "soc" node. Move the
L2 cache-controller there as well since it's the only one not following
this pattern.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200815182223.408965-1-martin.blumenstingl@googlemail.com
| -rw-r--r-- | arch/arm/boot/dts/meson.dtsi | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index eadb0832bcfc..7649dd1e0b9e 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -11,13 +11,6 @@ #size-cells = <1>; interrupt-parent = <&gic>; - L2: cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -172,6 +165,13 @@ }; }; + L2: cache-controller@c4200000 { + compatible = "arm,pl310-cache"; + reg = <0xc4200000 0x1000>; + cache-unified; + cache-level = <2>; + }; + periph: bus@c4300000 { compatible = "simple-bus"; reg = <0xc4300000 0x10000>; |