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| author | John Lin <john.lin@realtek.com> | 2015-11-16 14:41:07 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-11-16 13:17:01 +0000 |
| commit | 7336dcefac4d8f94fa205a668138a6462841acc4 (patch) | |
| tree | 4128e1ab1526bc2b7c9787f6abbbcd1ff13c096a | |
| parent | 2f64b6ed44c26eeb3d1bf5428936629cf552eda7 (diff) | |
| download | lwn-7336dcefac4d8f94fa205a668138a6462841acc4.tar.gz lwn-7336dcefac4d8f94fa205a668138a6462841acc4.zip | |
ASoC: rl6231: fix range of DMIC clock
The maximum DMIC clock rate is 3.072 MHz for most DMIC. And it will get better
performance in higher clock rate. If we set maximum to 3 MHz in driver, we will
get a clock rate which is not even close to 3 MHz.
For example, if DMIC clock source is 24.576 MHz, the DMIC clock will be about
1.5 MHz in current code. But it will be 3.072 MHz with this patch.
Signed-off-by: John Lin <john.lin@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | sound/soc/codecs/rl6231.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/codecs/rl6231.c b/sound/soc/codecs/rl6231.c index 18b42925314e..1dc68ab08a17 100644 --- a/sound/soc/codecs/rl6231.c +++ b/sound/soc/codecs/rl6231.c @@ -82,8 +82,8 @@ int rl6231_calc_dmic_clk(int rate) for (i = 0; i < ARRAY_SIZE(div); i++) { if ((div[i] % 3) == 0) continue; - /* find divider that gives DMIC frequency below 3MHz */ - if (3000000 * div[i] >= rate) + /* find divider that gives DMIC frequency below 3.072MHz */ + if (3072000 * div[i] >= rate) return i; } |