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author | Qi Tao <taoqi10@huawei.com> | 2024-01-26 17:38:25 +0800 |
---|---|---|
committer | Herbert Xu <herbert@gondor.apana.org.au> | 2024-02-02 18:10:05 +0800 |
commit | 68baa4289b8554998771799ed1f9695721e41a22 (patch) | |
tree | 34a79efcd6ea45b7feae54da077b13057f4b748d | |
parent | 4d314d27130b674a3687135fe94f44a40f107f76 (diff) | |
download | lwn-68baa4289b8554998771799ed1f9695721e41a22.tar.gz lwn-68baa4289b8554998771799ed1f9695721e41a22.zip |
crypto: hisilicon/sec2 - updates the sec DFX function register
As the sec DFX function is enhanced, some RAS registers are added
to the original DFX registers to enhance the DFX positioning function.
Signed-off-by: Qi Tao <taoqi10@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-rw-r--r-- | drivers/crypto/hisilicon/sec2/sec_main.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c index efa957ece23d..c290d8937b19 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -282,6 +282,11 @@ static const struct debugfs_reg32 sec_dfx_regs[] = { {"SEC_BD_SAA6 ", 0x301C38}, {"SEC_BD_SAA7 ", 0x301C3C}, {"SEC_BD_SAA8 ", 0x301C40}, + {"SEC_RAS_CE_ENABLE ", 0x301050}, + {"SEC_RAS_FE_ENABLE ", 0x301054}, + {"SEC_RAS_NFE_ENABLE ", 0x301058}, + {"SEC_REQ_TRNG_TIME_TH ", 0x30112C}, + {"SEC_CHANNEL_RNG_REQ_THLD ", 0x302110}, }; /* define the SEC's dfx regs region and region length */ |