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| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2016-02-22 11:43:39 +0000 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2016-07-12 08:48:01 -0400 |
| commit | 66e0e452e09345e95d7fa781d6d3c0c36c47b438 (patch) | |
| tree | 3dcf7216531ace00bf130a6f337ac2ccc04aea32 | |
| parent | 35807de76e1c2b7d15eea2f947983fcd043a2db0 (diff) | |
| download | lwn-66e0e452e09345e95d7fa781d6d3c0c36c47b438.tar.gz lwn-66e0e452e09345e95d7fa781d6d3c0c36c47b438.zip | |
clk: qcom: msm8960: fix ce3_core clk enable register
[ Upstream commit 732d6913691848db9fabaa6a25b4d6fad10ddccf ]
This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8960.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index 007534f7a2d7..5e3af78bf71b 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -2756,7 +2756,7 @@ static struct clk_branch ce3_core_clk = { .halt_reg = 0x2fdc, .halt_bit = 5, .clkr = { - .enable_reg = 0x36c4, + .enable_reg = 0x36cc, .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "ce3_core_clk", |