diff options
| author | Jonas Karlman <jonas@kwiboo.se> | 2023-01-10 22:55:50 +0000 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2023-01-11 11:19:21 +0100 |
| commit | 64b69474edf3b885c19a89bb165f978ba1b4be00 (patch) | |
| tree | 7ba02cc0de86299d08de12363c90339e22d36845 | |
| parent | 6fb13f888f2a6155fe4c19d14721e8909eda9b52 (diff) | |
| download | lwn-64b69474edf3b885c19a89bb165f978ba1b4be00.tar.gz lwn-64b69474edf3b885c19a89bb165f978ba1b4be00.zip | |
arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x
clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
and not to 32 kHz on RK356x.
Fix this by assigning clk_rtc_32k a rate of 32768, also assign the parent
to clk_rtc32k_frac.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230110225547.1563119-2-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 5706c3e24f0a..e319699f5e39 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -422,8 +422,9 @@ clock-names = "xin24m"; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; - assigned-clock-rates = <1200000000>, <200000000>; + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; + assigned-clock-rates = <32768>, <1200000000>, <200000000>; + assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; rockchip,grf = <&grf>; }; |